mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 16:42:33 +00:00
83bdd501a3
BFCSEL's else-target turned out to be the implicit fall-through, so the BF_BELSE operand encoding, the BFCSEL_ELSE_T32 relocation, and their encoder/decoder cases were never referenced by any table entry. Remove them. Also restructure the MSA COPY specgen loop so COPY_U only iterates .B/.H (COPY_U.W is mips64-only and emitted in the mips64 section), which drops the spurious 'skipped COPY_U_W' message. No functional change to any generated encode form; arm64/arm32/mips all still 100%, 461/600/281 tests green.
402 lines
21 KiB
Lua
402 lines
21 KiB
Lua
#!/usr/bin/env luajit
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-- rexcode · Brendan Punsky (dotbmp@github), original author
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--
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-- Encode-form spec generator (MIPS / MSA). Expands compact per-family specs
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-- into ENCODING_TABLE entries, deriving `bits` from llvm-mc (the oracle) and
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-- `mask` empirically: assemble each form all-zero, then one variant per operand
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-- field at its max register, and mask = ~(union of the deltas). MIPS words are
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-- big-endian. Each MSA element format (.B/.H/.W/.D) is a distinct mnemonic
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-- (e.g. FADD_W / FADD_D), so the data-format suffix is part of the name.
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--
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-- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin.
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--
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-- Run: luajit tablegen/specgen.lua (from mips/, or with a full path)
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local bit = require("bit")
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local LLVM = "llvm-mc --assemble --triple=mips --mattr=+msa,+dsp,+dspr2,+mips32r2,+fp64 --show-encoding"
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local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "."
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local TABLE = DIR .. "/encoding_table.odin"
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local function word(line, cmd)
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local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, cmd or LLVM))
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local out = p:read("*a"); p:close()
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local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)")
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if not b1 then return nil end
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return tonumber(b1..b2..b3..b4, 16) -- big-endian: first byte is MSB
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end
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-- Paired-single / mips64 forms need a 64-bit-capable assembler invocation.
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local LLVM_PS = "llvm-mc --assemble --triple=mips64 -mcpu=mips64r2 --show-encoding"
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local LLVM_64 = "llvm-mc --assemble --triple=mips64 --mattr=+msa,+mips64r6 --show-encoding"
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local function mask_of(base, variants)
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local x = 0
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for _, w in ipairs(variants) do x = bit.bor(x, bit.bxor(base, w)) end
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return bit.band(bit.bnot(x), 0xFFFFFFFF)
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end
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local sections, skips, n_forms = {}, {}, 0
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-- Emit one mnemonic's single-form entry from an asm builder + per-field maxes.
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-- ops/enc are the prebuilt "{.A,.B,.C,.NONE}" text. asm(vals) returns the asm
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-- (vals[i] = register number for field i); maxes[i] = max register for field i.
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local function entry(mnem, ops, enc, feat, asm, maxes, cmd)
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local zero = {}; for i=1,#maxes do zero[i]=0 end
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local b0 = word(asm(zero), cmd)
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if not b0 then skips[#skips+1]=mnem; return nil end
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local vs = {}
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for i=1,#maxes do
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local v={}; for j=1,#maxes do v[j]=0 end; v[i]=maxes[i]
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local w=word(asm(v), cmd); if not w then skips[#skips+1]=mnem; return nil end; vs[#vs+1]=w
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end
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n_forms = n_forms + 1
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return string.format(" .%s = { {.%s, %s, %s, 0x%s, 0x%s, .%s, {}} },",
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mnem, mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), feat)
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end
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-- A vector 3-register family: Wd, Ws, Wt (each a .B/.H/.W/.D variant).
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local OPS3 = "{.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}"
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local ENC3 = "{.WD,.WS,.WT,.NONE}"
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local OPS2 = "{.MSA_VEC,.MSA_VEC,.NONE,.NONE}"
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local ENC2 = "{.WD,.WS,.NONE,.NONE}"
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-- emit a family across data-format suffixes.
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-- base = uppercase stem (FADD); low = lowercase asm stem (fadd)
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-- dfs = list of {SUFFIX, asm_token} (e.g. {"W","w"})
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-- three = 3-register (else 2-register)
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local function family(base, low, dfs, three)
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local rows = {}
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local ops = three and OPS3 or ENC3 and (three and OPS3 or OPS2)
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for _, d in ipairs(dfs) do
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local mnem = base .. "_" .. d[1]
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local function asm(v)
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if three then return string.format("%s.%s $w%d,$w%d,$w%d", low, d[2], v[1], v[2], v[3]) end
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return string.format("%s.%s $w%d,$w%d", low, d[2], v[1], v[2])
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end
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local r = entry(mnem, three and OPS3 or OPS2, three and ENC3 or ENC2, "MSA", asm, three and {31,31,31} or {31,31})
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if r then rows[#rows+1] = r end
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end
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for _, r in ipairs(rows) do sections[#sections+1] = r end
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end
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local WD = {{"W","w"},{"D","d"}} -- 3RF / 2RF data formats
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local HWD = {{"H","h"},{"W","w"},{"D","d"}} -- 3R (no byte) data formats
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local BHWD = {{"B","b"},{"H","h"},{"W","w"},{"D","d"}}
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-- ---- 3RF: vector floating-point arithmetic / compare (Wd, Ws, Wt; .W/.D) ----
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for _, b in ipairs({
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{"FADD","fadd"},{"FSUB","fsub"},{"FMUL","fmul"},{"FDIV","fdiv"},
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{"FMAX","fmax"},{"FMIN","fmin"},
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{"FCEQ","fceq"},{"FCLE","fcle"},{"FCLT","fclt"},{"FCNE","fcne"},
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}) do family(b[1], b[2], WD, true) end
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-- ---- 3R: signed/unsigned dot product (Wd, Ws, Wt; .H/.W/.D) -----------------
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for _, b in ipairs({{"DOTP_S","dotp_s"},{"DOTP_U","dotp_u"}}) do family(b[1], b[2], HWD, true) end
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-- ---- VEC: bit-select (no data format) --------------------------------------
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for _, b in ipairs({{"BMNZ_V","bmnz.v"},{"BMZ_V","bmz.v"},{"BSEL_V","bsel.v"}}) do
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local r = entry(b[1], OPS3, ENC3, "MSA", function(v) return string.format("%s $w%d,$w%d,$w%d", b[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1] = r end
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end
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-- ---- 2R: count leading ones/zeros, popcount (Wd, Ws; .B/.H/.W/.D) -----------
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for _, b in ipairs({{"NLOC","nloc"},{"NLZC","nlzc"},{"PCNT","pcnt"}}) do family(b[1], b[2], BHWD, false) end
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-- ---- 2RF: vector floating-point one-source (Wd, Ws; .W/.D) ------------------
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for _, b in ipairs({
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{"FSQRT","fsqrt"},{"FRSQRT","frsqrt"},{"FRCP","frcp"},{"FRINT","frint"},
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{"FTRUNC_S","ftrunc_s"},{"FTRUNC_U","ftrunc_u"},{"FFINT_S","ffint_s"},{"FFINT_U","ffint_u"},
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}) do family(b[1], b[2], WD, false) end
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-- ---- BIT: shift by immediate (Wd, Ws, m) -- marker per df in `bits` --------
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local BIT_SH = {b=7, h=15, w=31, d=63}
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for _, base in ipairs({{"SLLI","slli"},{"SRAI","srai"},{"SRLI","srli"}}) do
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for _, d in ipairs(BHWD) do
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local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_BIT_SHIFT,.NONE}", "MSA",
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function(v) return string.format("%s.%s $w%d,$w%d,%d", base[2], d[2], v[1], v[2], v[3]) end, {31,31,BIT_SH[d[2]]})
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if r then sections[#sections+1]=r end
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end
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end
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-- ---- ELM: element broadcast/insert by immediate index (Wd, Ws[idx]) --------
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local ELM_IDX = {b=15, h=7, w=3, d=1}
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for _, base in ipairs({{"SPLATI","splati"},{"SLDI","sldi"}}) do
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for _, d in ipairs(BHWD) do
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local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
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function(v) return string.format("%s.%s $w%d,$w%d[%d]", base[2], d[2], v[1], v[2], v[3]) end, {31,31,ELM_IDX[d[2]]})
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if r then sections[#sections+1]=r end
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end
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end
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-- ---- VSHF (3R vector shuffle) ----------------------------------------------
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for _, d in ipairs(BHWD) do
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local r = entry("VSHF_"..d[1], OPS3, ENC3, "MSA",
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function(v) return string.format("vshf.%s $w%d,$w%d,$w%d", d[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- SPLAT / SLD (element broadcast/slide by GPR index) --------------------
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for _, base in ipairs({{"SPLAT","splat"},{"SLD","sld"}}) do
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for _, d in ipairs(BHWD) do
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local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.GPR,.NONE}", "{.WD,.WS,.RT,.NONE}", "MSA",
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function(v) return string.format("%s.%s $w%d,$w%d[$%d]", base[2], d[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1]=r end
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end
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end
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-- ---- I8: 8-bit-immediate logical / shuffle ---------------------------------
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for _, base in ipairs({{"ANDI_B","andi.b"},{"ORI_B","ori.b"},{"XORI_B","xori.b"},{"NORI_B","nori.b"},
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{"BMNZI_B","bmnzi.b"},{"BMZI_B","bmzi.b"},{"BSELI_B","bseli.b"}}) do
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local r = entry(base[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_I8,.NONE}", "MSA",
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function(v) return string.format("%s $w%d,$w%d,%d", base[2], v[1], v[2], v[3]) end, {31,31,255})
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if r then sections[#sections+1]=r end
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end
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for _, d in ipairs({{"B","b"},{"H","h"},{"W","w"}}) do
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local r = entry("SHF_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_I8,.NONE}", "MSA",
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function(v) return string.format("shf.%s $w%d,$w%d,%d", d[2], v[1], v[2], v[3]) end, {31,31,255})
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if r then sections[#sections+1]=r end
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end
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-- ---- INSVE: element insert from Ws[0] into Wd[idx] -------------------------
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for _, d in ipairs(BHWD) do
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local r = entry("INSVE_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
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function(v) return string.format("insve.%s $w%d[%d],$w%d[0]", d[2], v[1], v[3], v[2]) end, {31,31,ELM_IDX[d[2]]})
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if r then sections[#sections+1]=r end
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end
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-- ---- DSP ASE three-register (Rd, Rs, Rt) -----------------------------------
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local GPR3 = "{.GPR,.GPR,.GPR,.NONE}"
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local ENC_RDST = "{.RD,.RS,.RT,.NONE}"
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for _, b in ipairs({
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{"ADDU_PH","addu.ph"},{"ADDU_S_PH","addu_s.ph"},{"SUBU_PH","subu.ph"},{"SUBU_S_PH","subu_s.ph"},
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{"MULEQ_S_W_PHL","muleq_s.w.phl"},{"MULEQ_S_W_PHR","muleq_s.w.phr"},
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{"MULEU_S_PH_QBL","muleu_s.ph.qbl"},{"MULEU_S_PH_QBR","muleu_s.ph.qbr"},
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{"MULQ_RS_PH","mulq_rs.ph"},{"MULQ_S_PH","mulq_s.ph"},
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{"PRECRQ_PH_W","precrq.ph.w"},{"PRECRQ_QB_PH","precrq.qb.ph"},
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{"PRECRQ_RS_PH_W","precrq_rs.ph.w"},{"PRECRQU_S_QB_PH","precrqu_s.qb.ph"},
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{"PICK_PH","pick.ph"},{"PICK_QB","pick.qb"},
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{"CMPGU_EQ_QB","cmpgu.eq.qb"},{"CMPGU_LE_QB","cmpgu.le.qb"},{"CMPGU_LT_QB","cmpgu.lt.qb"},
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}) do
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local r = entry(b[1], GPR3, ENC_RDST, "DSP_R2", function(v) return string.format("%s $%d,$%d,$%d", b[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- DSP ASE variable shifts: Rd, Rt (value), Rs (shift) -> enc {RD,RT,RS} --
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for _, b in ipairs({
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{"SHLLV_PH","shllv.ph"},{"SHLLV_S_PH","shllv_s.ph"},{"SHLLV_S_W","shllv_s.w"},
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{"SHRAV_PH","shrav.ph"},{"SHRAV_QB","shrav.qb"},{"SHRAV_R_PH","shrav_r.ph"},
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{"SHRAV_R_QB","shrav_r.qb"},{"SHRAV_R_W","shrav_r.w"},{"SHRLV_PH","shrlv.ph"},
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}) do
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local r = entry(b[1], GPR3, "{.RD,.RT,.RS,.NONE}", "DSP_R2", function(v) return string.format("%s $%d,$%d,$%d", b[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- DSP ASE compare (Rs, Rt -> DSP flags) ---------------------------------
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for _, b in ipairs({
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{"CMP_EQ_PH","cmp.eq.ph"},{"CMP_LE_PH","cmp.le.ph"},{"CMP_LT_PH","cmp.lt.ph"},
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{"CMPU_EQ_QB","cmpu.eq.qb"},{"CMPU_LE_QB","cmpu.le.qb"},{"CMPU_LT_QB","cmpu.lt.qb"},
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}) do
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local r = entry(b[1], "{.GPR,.GPR,.NONE,.NONE}", "{.RS,.RT,.NONE,.NONE}", "DSP_R2",
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function(v) return string.format("%s $%d,$%d", b[2], v[1], v[2]) end, {31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- FPU conditional move (S/D) -------------------------------------------
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for _, b in ipairs({{"MOVN","movn"},{"MOVZ","movz"}}) do
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for _, f in ipairs({{"S","s","FPR_S"},{"D","d","FPR_D"}}) do
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local r = entry(b[1].."_"..f[1], "{."..f[3]..",."..f[3]..",.GPR,.NONE}", "{.FD,.FS,.RT,.NONE}", "FPU",
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function(v) return string.format("%s.%s $f%d,$f%d,$%d", b[2], f[2], v[1], v[2], v[3]) end, {31,31,31})
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if r then sections[#sections+1]=r end
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end
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end
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for _, b in ipairs({{"MOVF","movf"},{"MOVT","movt"}}) do
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for _, f in ipairs({{"S","s","FPR_S"},{"D","d","FPR_D"}}) do
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local r = entry(b[1].."_"..f[1], "{."..f[3]..",."..f[3]..",.FCC,.NONE}", "{.FD,.FS,.FCC_BC,.NONE}", "FPU",
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function(v) return string.format("%s.%s $f%d,$f%d,$fcc%d", b[2], f[2], v[1], v[2], v[3]) end, {31,31,7})
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if r then sections[#sections+1]=r end
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end
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end
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-- ---- FPU convert to FP (FCVT_x_y = cvt.x.y) --------------------------------
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for _, b in ipairs({{"FCVT_D_W","cvt.d.w","FPR_D","FPR_W"},{"FCVT_S_D","cvt.s.d","FPR_S","FPR_D"},{"FCVT_S_W","cvt.s.w","FPR_S","FPR_W"}}) do
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local r = entry(b[1], "{."..b[3]..",."..b[4]..",.NONE,.NONE}", "{.FD,.FS,.NONE,.NONE}", "FPU",
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function(v) return string.format("%s $f%d,$f%d", b[2], v[1], v[2]) end, {31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- DSP ASE two-register (Rd, Rt) ----------------------------------------
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for _, b in ipairs({
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{"PRECEQU_PH_QBLA","precequ.ph.qbla"},{"PRECEQU_PH_QBRA","precequ.ph.qbra"},
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{"PRECEU_PH_QBLA","preceu.ph.qbla"},{"PRECEU_PH_QBRA","preceu.ph.qbra"},
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{"REPLV_PH","replv.ph"},{"REPLV_QB","replv.qb"},
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}) do
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local r = entry(b[1], "{.GPR,.GPR,.NONE,.NONE}", "{.RD,.RT,.NONE,.NONE}", "DSP_R2",
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function(v) return string.format("%s $%d,$%d", b[2], v[1], v[2]) end, {31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- FPU fused multiply-add (COP1X 4-register: fd, fr, fs, ft) -------------
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for _, b in ipairs({{"MADD","madd"},{"MSUB","msub"},{"NMADD","nmadd"},{"NMSUB","nmsub"}}) do
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for _, f in ipairs({{"S","s","FPR_S"},{"D","d","FPR_D"}}) do
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local r = entry(b[1].."_"..f[1], "{."..f[3]..",."..f[3]..",."..f[3]..",."..f[3].."}", "{.FD,.FR,.FS,.FT}", "FPU",
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function(v) return string.format("%s.%s $f%d,$f%d,$f%d,$f%d", b[2], f[2], v[1], v[2], v[3], v[4]) end, {31,31,31,31})
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if r then sections[#sections+1]=r end
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end
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end
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-- ---- MSA COPY (vector lane -> GPR) and INSERT (GPR -> vector lane) ----------
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-- COPY_S has .B/.H/.W; COPY_U only .B/.H on mips32 (COPY_U.W is a mips64-only
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-- form, emitted in the mips64 section below).
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for _, c in ipairs({{"COPY_S","copy_s",{{"B","b",15},{"H","h",7},{"W","w",3}}}, {"COPY_U","copy_u",{{"B","b",15},{"H","h",7}}}}) do
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for _, d in ipairs(c[3]) do
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local r = entry(c[1].."_"..d[1], "{.GPR,.MSA_VEC,.IMM5,.NONE}", "{.GPR_AT_6,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
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function(v) return string.format("%s.%s $%d,$w%d[%d]", c[2], d[2], v[1], v[2], v[3]) end, {31,31,d[3]})
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if r then sections[#sections+1]=r end
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end
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end
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for _, d in ipairs({{"B","b",15},{"H","h",7},{"W","w",3}}) do
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local r = entry("INSERT_"..d[1], "{.MSA_VEC,.GPR,.IMM5,.NONE}", "{.WD,.GPR_AT_11,.MSA_ELM_IDX,.NONE}", "MSA",
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function(v) return string.format("insert.%s $w%d[%d],$%d", d[2], v[1], v[3], v[2]) end, {31,31,d[3]})
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if r then sections[#sections+1]=r end
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end
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-- ---- Misc control: DI/EI (rt), RDHWR (rt, rd) ------------------------------
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for _, b in ipairs({{"DI","di"},{"EI","ei"}}) do
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local r = entry(b[1], "{.GPR,.NONE,.NONE,.NONE}", "{.RT,.NONE,.NONE,.NONE}", "MIPS32_R2",
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function(v) return string.format("%s $%d", b[2], v[1]) end, {31})
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if r then sections[#sections+1]=r end
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end
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do
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local r = entry("RDHWR", "{.GPR,.GPR,.NONE,.NONE}", "{.RT,.RD,.NONE,.NONE}", "MIPS32_R2",
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function(v) return string.format("rdhwr $%d,$%d", v[1], v[2]) end, {31,31})
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if r then sections[#sections+1]=r end
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end
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-- ---- DSP ASE shift by immediate (Rd, Rt, sa) ------------------------------
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for _, b in ipairs({{"SHRA_QB","shra.qb",7},{"SHRA_R_QB","shra_r.qb",7},{"SHRA_R_PH","shra_r.ph",15},{"SHRL_PH","shrl.ph",15}}) do
|
|
local r = entry(b[1], "{.GPR,.GPR,.IMM5,.NONE}", "{.RD,.RT,.DSP_SA,.NONE}", "DSP_R2",
|
|
function(v) return string.format("%s $%d,$%d,%d", b[2], v[1], v[2], v[3]) end, {31,31,b[3]})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
|
|
-- ---- DSP ASE accumulator ops (ac0..ac3 at bits 12:11, modeled as imm) ------
|
|
for _, b in ipairs({
|
|
{"DPA_W_PH","dpa.w.ph"},{"DPAX_W_PH","dpax.w.ph"},{"DPS_W_PH","dps.w.ph"},{"DPSX_W_PH","dpsx.w.ph"},
|
|
{"MAQ_S_W_PHL","maq_s.w.phl"},{"MAQ_S_W_PHR","maq_s.w.phr"},{"MAQ_SA_W_PHL","maq_sa.w.phl"},{"MAQ_SA_W_PHR","maq_sa.w.phr"},
|
|
}) do
|
|
local r = entry(b[1], "{.IMM5,.GPR,.GPR,.NONE}", "{.AC_NUM,.RS,.RT,.NONE}", "DSP_R2",
|
|
function(v) return string.format("%s $ac%d,$%d,$%d", b[2], v[1], v[2], v[3]) end, {3,31,31})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
do
|
|
local r = entry("MTHLIP", "{.GPR,.IMM5,.NONE,.NONE}", "{.RS,.AC_NUM,.NONE,.NONE}", "DSP_R2",
|
|
function(v) return string.format("mthlip $%d,$ac%d", v[1], v[2]) end, {31,3})
|
|
if r then sections[#sections+1]=r end
|
|
r = entry("SHILOV", "{.IMM5,.GPR,.NONE,.NONE}", "{.AC_NUM,.RS,.NONE,.NONE}", "DSP_R2",
|
|
function(v) return string.format("shilov $ac%d,$%d", v[1], v[2]) end, {3,31})
|
|
if r then sections[#sections+1]=r end
|
|
-- SHILO immediate is signed 6-bit; vary to -1 so all six field bits toggle.
|
|
r = entry("SHILO", "{.IMM5,.IMM5,.NONE,.NONE}", "{.AC_NUM,.SHILO_IMM,.NONE,.NONE}", "DSP_R2",
|
|
function(v) return string.format("shilo $ac%d,%d", v[1], v[2]) end, {3,-1})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
|
|
-- ---- Paired-single FP (needs a 64-bit FPU; assembled via mips64r2) ---------
|
|
do
|
|
local r = entry("CVT_PS_S", "{.FPR_PS,.FPR_S,.FPR_S,.NONE}", "{.FD,.FS,.FT,.NONE}", "FPU",
|
|
function(v) return string.format("cvt.ps.s $f%d,$f%d,$f%d", v[1], v[2], v[3]) end, {31,31,31}, LLVM_PS)
|
|
if r then sections[#sections+1]=r end
|
|
for _, b in ipairs({{"CVT_S_PL","cvt.s.pl"},{"CVT_S_PU","cvt.s.pu"}}) do
|
|
r = entry(b[1], "{.FPR_S,.FPR_PS,.NONE,.NONE}", "{.FD,.FS,.NONE,.NONE}", "FPU",
|
|
function(v) return string.format("%s $f%d,$f%d", b[2], v[1], v[2]) end, {31,31}, LLVM_PS)
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
for _, b in ipairs({{"PLL_PS","pll.ps"},{"PLU_PS","plu.ps"},{"PUL_PS","pul.ps"},{"PUU_PS","puu.ps"}}) do
|
|
r = entry(b[1], "{.FPR_PS,.FPR_PS,.FPR_PS,.NONE}", "{.FD,.FS,.FT,.NONE}", "FPU",
|
|
function(v) return string.format("%s $f%d,$f%d,$f%d", b[2], v[1], v[2], v[3]) end, {31,31,31}, LLVM_PS)
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
end
|
|
|
|
-- ---- mips64-only MSA element ops (assembled via the mips64 triple) ----------
|
|
do
|
|
local r = entry("INSERT_D", "{.MSA_VEC,.GPR,.IMM5,.NONE}", "{.WD,.GPR_AT_11,.MSA_ELM_IDX,.NONE}", "MSA",
|
|
function(v) return string.format("insert.d $w%d[%d],$%d", v[1], v[3], v[2]) end, {31,31,1}, LLVM_64)
|
|
if r then sections[#sections+1]=r end
|
|
r = entry("COPY_U_W", "{.GPR,.MSA_VEC,.IMM5,.NONE}", "{.GPR_AT_6,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
|
|
function(v) return string.format("copy_u.w $%d,$w%d[%d]", v[1], v[2], v[3]) end, {31,31,3}, LLVM_64)
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
|
|
-- ---- DSP ASE replicate immediate (Rd <- broadcast imm) --------------------
|
|
-- REPL.PH = signed 10-bit at 25:16 (reuse MSA_S10); REPL.QB = 8-bit at 23:16
|
|
-- (reuse MSA_I8). Vary REPL.PH's imm to -1 so all ten field bits toggle.
|
|
do
|
|
local r = entry("REPL_PH", "{.GPR,.IMM5,.NONE,.NONE}", "{.RD,.MSA_S10,.NONE,.NONE}", "DSP_R1",
|
|
function(v) return string.format("repl.ph $%d,%d", v[1], v[2]) end, {31,-1})
|
|
if r then sections[#sections+1]=r end
|
|
r = entry("REPL_QB", "{.GPR,.IMM5,.NONE,.NONE}", "{.RD,.MSA_I8,.NONE,.NONE}", "DSP_R1",
|
|
function(v) return string.format("repl.qb $%d,%d", v[1], v[2]) end, {31,255})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
|
|
-- ---- DSP ASE extract-from-accumulator ops ---------------------------------
|
|
do
|
|
local r = entry("EXTPDP", "{.GPR,.IMM5,.IMM5,.NONE}", "{.RT,.AC_NUM,.EXT_SIZE,.NONE}", "DSP_R2",
|
|
function(v) return string.format("extpdp $%d,$ac%d,%d", v[1], v[2], v[3]) end, {31,3,31})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
for _, b in ipairs({{"EXTPDPV","extpdpv"},{"EXTRV_R_W","extrv_r.w"},{"EXTRV_RS_W","extrv_rs.w"},{"EXTRV_S_H","extrv_s.h"}}) do
|
|
local r = entry(b[1], "{.GPR,.IMM5,.GPR,.NONE}", "{.RT,.AC_NUM,.RS,.NONE}", "DSP_R2",
|
|
function(v) return string.format("%s $%d,$ac%d,$%d", b[2], v[1], v[2], v[3]) end, {31,3,31})
|
|
if r then sections[#sections+1]=r end
|
|
end
|
|
|
|
-- ---- Branches: derive bits/regs, then mark the PC-relative offset variable.
|
|
-- Compact (R6) branches need the r6 ISA, so each family passes its own mattr.
|
|
local function branch_block(mnem, ops, enc, feat, asm, maxes, offbits, cmd)
|
|
local zero={}; for i=1,#maxes do zero[i]=0 end
|
|
local b0 = word(asm(zero), cmd)
|
|
if not b0 then skips[#skips+1]=mnem; return end
|
|
local vs={}
|
|
for i=1,#maxes do
|
|
local v={}; for j=1,#maxes do v[j]=0 end; v[i]=maxes[i]
|
|
local w=word(asm(v), cmd); if not w then skips[#skips+1]=mnem; return end; vs[#vs+1]=w
|
|
end
|
|
local m = bit.band(mask_of(b0,vs), bit.bnot((2^offbits)-1)) -- offset field = variable
|
|
n_forms=n_forms+1
|
|
sections[#sections+1]=string.format(" .%s = { {.%s, %s, %s, 0x%s, 0x%s, .%s, {}} },",
|
|
mnem, mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(m):upper(), feat)
|
|
end
|
|
local LLVM_MSA = "llvm-mc --assemble --triple=mips --mattr=+msa --show-encoding"
|
|
local LLVM_R6 = "llvm-mc --assemble --triple=mips --mattr=+mips32r6 --show-encoding"
|
|
local LLVM_64R6 = "llvm-mc --assemble --triple=mips64 --mattr=+mips64r6 --show-encoding"
|
|
|
|
-- NOTE: the R6 two-/one-register compact branches (BEQC/BNEC/BLTC/BGEC/BLTUC/
|
|
-- BGEUC/BLEZC/BGTZC/BGEZC/BLTZC) are intentionally NOT generated here. They
|
|
-- pack into shared "POP" major opcodes (e.g. BGEC/BLTC/BLEZC/BGEZC all live in
|
|
-- 0x58/0x5C) and are disambiguated only by the rs/rt *relationship* (rs==rt,
|
|
-- rs==0, rs<rt) -- which the opcode+mask decode model cannot express without
|
|
-- operand-aware logic. Deferred until the decoder grows POP-branch handling.
|
|
for _, b in ipairs({{"BZ","bz"},{"BNZ","bnz"}}) do
|
|
for _, d in ipairs({{"B","b"},{"H","h"},{"W","w"},{"D","d"},{"V","v"}}) do
|
|
branch_block(b[1].."_"..d[1], "{.MSA_VEC,.REL16,.NONE,.NONE}", "{.WT,.BRANCH_16,.NONE,.NONE}", "MSA",
|
|
function(v) return string.format("%s.%s $w%d,0", b[2], d[2], v[1]) end, {31}, 16, LLVM_MSA)
|
|
end
|
|
end
|
|
|
|
-- ---- R6 PC-relative loads (offset is a 19-/18-bit PC-relative label) --------
|
|
branch_block("LWPC", "{.GPR,.REL19,.NONE,.NONE}", "{.RS,.BRANCH_19,.NONE,.NONE}", "MIPS32_R6",
|
|
function(v) return string.format("lwpc $%d,0", v[1]) end, {31}, 19, LLVM_R6)
|
|
branch_block("LWUPC", "{.GPR,.REL19,.NONE,.NONE}", "{.RS,.BRANCH_19,.NONE,.NONE}", "MIPS64_R6",
|
|
function(v) return string.format("lwupc $%d,0", v[1]) end, {31}, 19, LLVM_64R6)
|
|
branch_block("LDPC", "{.GPR,.REL18,.NONE,.NONE}", "{.RS,.BRANCH_18,.NONE,.NONE}", "MIPS64_R6",
|
|
function(v) return string.format("ldpc $%d,0", v[1]) end, {31}, 18, LLVM_64R6)
|
|
|
|
-- ---- splice into the SoT ---------------------------------------------------
|
|
local region = " // SPECGEN:BEGIN\n" .. table.concat(sections, "\n") .. "\n // SPECGEN:END"
|
|
local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close()
|
|
local new, n = src:gsub(" // SPECGEN:BEGIN.- // SPECGEN:END", (region:gsub("%%", "%%%%")))
|
|
if n ~= 1 then io.stderr:write("FATAL: expected one SPECGEN region, found "..n.."\n"); os.exit(1) end
|
|
local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close()
|
|
io.write(string.format("specgen(mips): wrote %d forms\n", n_forms))
|
|
if #skips > 0 then io.write(" skipped "..#skips.." form(s): "..table.concat(skips, " ").."\n") end
|