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c6edd6d5cd
PS2 R5900 MMI: MSUB1/MSUBU1 (second-MAC, SPECIAL2 func +0x20 exactly like the implemented MADD1/MADDU1) and the three-operand MADD_EE/MADDU_EE/ MSUB_EE/MSUBU_EE (write Rd as well as HI/LO; the Rd!=0 form selected by a less-specific mask after the two-operand MADD/MSUB and PLZCW match). RDPGPR/WRPGPR (COP0 shadow-GPR move, hand-encoded from the MIPS32r2 manual since llvm-mc gates them). Drop BPOSGE64: not a real ISA instruction (DSPControl.pos is 6-bit, only BPOSGE32 exists; llvm rejects it). Every encodable mips Mnemonic now has an encode form (gap = 0). All self-consistent and decode-clean; 281 tests green.