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https://github.com/odin-lang/Odin.git
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fe7b81d64f
Remove from the Mnemonic enum: LDARB_X/LDARH_X/STLRB_X/STLRH_X (no
distinct byte/half acquire-release 'X' encoding exists -- LDARB/LDARH/
STLRB/STLRH already cover them), and the 12 redundant SME names
SME_LD1{B,H,W,D,Q}_ZA / SME_ST1{...}_ZA / SME_MOVA_TO_Z / SME_MOVA_TO_ZA
(same instructions as the canonical *_TILE / MOVA_*_FROM_* forms).
The builder generator now emits delegating aliases for the redundant SME
names (inst_sme_ld1b_za :: inst_sme_ld1b_tile, ...), so the convenient
names keep working and resolve to the canonical, decode-unambiguous
encodings. With XAR_Z landed, the arm64 Mnemonic enum is now 100%
covered: every entry has an encode form. 461 tests green.
4475 lines
576 KiB
Odin
4475 lines
576 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS.
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// Regenerate with: odin run arm64/tools/gen_mnemonic_builders.odin -file
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//
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// Typed mnemonic builder procedures with overloading. Every mnemonic that has
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// at least one encode form gets an inst_* (returns Instruction) and emit_*
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// (appends to a [dynamic]Instruction) overload group covering all of its
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// distinct operand SHAPES. Forms that share an Odin signature (e.g. the W/X
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// variants, or NEON arrangement / SVE element-size variants which are all
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// passed as a Register/u8) collapse to one builder; the encoder's matcher
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// disambiguates by register class / size at encode time.
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// =============================================================================
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// Individual Typed Builder Procedures
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// =============================================================================
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inst_add_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD_IMM, dst, src, imm) }
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emit_add_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_imm_r_r_i(dst, src, imm)) }
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inst_adds_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS_IMM, dst, src, imm) }
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emit_adds_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_imm_r_r_i(dst, src, imm)) }
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inst_sub_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB_IMM, dst, src, imm) }
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emit_sub_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_imm_r_r_i(dst, src, imm)) }
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inst_subs_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS_IMM, dst, src, imm) }
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emit_subs_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_imm_r_r_i(dst, src, imm)) }
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inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} }
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emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) }
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inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} }
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emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) }
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inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} }
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emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) }
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inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} }
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emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) }
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inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} }
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emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) }
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inst_add_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_add_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_adds_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_adds_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_sub_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_sub_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_subs_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_subs_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_and_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_and_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_ands_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_ands_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_orr_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_orr_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_eor_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_eor_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_bic_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_bic_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_bics_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_bics_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_orn_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_orn_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_eon_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} }
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emit_eon_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) }
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inst_add_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} }
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emit_add_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) }
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inst_adds_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} }
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emit_adds_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) }
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inst_sub_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} }
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emit_sub_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) }
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inst_subs_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} }
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emit_subs_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) }
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inst_lslv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSLV, dst, src, src2) }
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emit_lslv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lslv_r_r_r(dst, src, src2)) }
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inst_lsrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSRV, dst, src, src2) }
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emit_lsrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsrv_r_r_r(dst, src, src2)) }
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inst_asrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASRV, dst, src, src2) }
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emit_asrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asrv_r_r_r(dst, src, src2)) }
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inst_rorv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.RORV, dst, src, src2) }
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emit_rorv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rorv_r_r_r(dst, src, src2)) }
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inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) }
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emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) }
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inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) }
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emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) }
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inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) }
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emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) }
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inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) }
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emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) }
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inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) }
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emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) }
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inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) }
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emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) }
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inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) }
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emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) }
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inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) }
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emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) }
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inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) }
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emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) }
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inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) }
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emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) }
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inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) }
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emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) }
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inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) }
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emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) }
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inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) }
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emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) }
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inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) }
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emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) }
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inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) }
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emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) }
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inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) }
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emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) }
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inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) }
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inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) }
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inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) }
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inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) }
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inst_ccmp_reg_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP_REG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} }
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emit_ccmp_reg_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_reg_r_r_i_c(dst, src, imm, cond)) }
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inst_ccmp_imm_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP_IMM, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} }
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emit_ccmp_imm_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_imm_r_i_i_c(dst, imm, imm2, cond)) }
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inst_ccmn_reg_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN_REG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} }
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emit_ccmn_reg_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_reg_r_r_i_c(dst, src, imm, cond)) }
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inst_ccmn_imm_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN_IMM, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} }
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emit_ccmn_imm_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_imm_r_i_i_c(dst, imm, imm2, cond)) }
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inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} }
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emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) }
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inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) }
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emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) }
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inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) }
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emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) }
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inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) }
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emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) }
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inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) }
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emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) }
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inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) }
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inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) }
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emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) }
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emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) }
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inst_b_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} }
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emit_b_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_b_cond_c_l(cond, label)) }
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inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} }
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emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) }
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inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} }
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emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) }
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inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} }
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emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) }
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inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} }
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emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) }
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inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) }
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emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) }
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inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) }
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emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) }
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inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) }
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emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) }
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inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) }
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emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) }
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inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) }
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emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) }
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inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) }
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emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) }
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inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) }
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emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) }
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inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) }
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emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) }
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inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) }
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emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) }
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inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) }
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emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) }
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inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) }
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emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) }
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inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) }
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emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) }
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inst_ldr_lit_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR_LIT, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} }
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emit_ldr_lit_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_lit_r_l(dst, label)) }
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inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) }
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emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) }
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inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) }
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emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) }
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inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) }
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emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) }
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inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) }
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emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) }
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inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) }
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emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) }
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inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) }
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emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) }
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inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) }
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emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) }
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inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) }
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emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) }
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inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) }
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emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) }
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inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) }
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emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) }
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inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) }
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emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) }
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inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) }
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emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) }
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inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) }
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emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) }
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inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) }
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emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) }
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inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) }
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emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) }
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inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) }
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emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) }
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inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} }
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emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) }
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inst_mrs_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MRS, dst, imm) }
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emit_mrs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_i(dst, imm)) }
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inst_msr_imm_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR_IMM, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} }
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emit_msr_imm_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_imm_i_i(imm, imm2)) }
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inst_msr_reg_i_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR_REG, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_reg(src), {}, {}}} }
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emit_msr_reg_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_reg_i_r(imm, src)) }
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inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} }
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emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) }
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inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} }
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emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) }
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inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} }
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emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) }
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inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) }
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inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) }
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inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) }
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inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) }
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inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) }
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inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) }
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emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) }
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inst_fmov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_REG, dst, src) }
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emit_fmov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_reg_r_r(dst, src)) }
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inst_fmov_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV_IMM, dst, imm) }
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emit_fmov_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_imm_r_i(dst, imm)) }
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inst_fmov_gen_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_GEN, dst, src) }
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emit_fmov_gen_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_gen_r_r(dst, src)) }
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inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) }
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emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) }
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inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) }
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emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) }
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inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) }
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emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) }
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inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) }
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emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) }
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inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) }
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emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) }
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inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) }
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emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) }
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inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) }
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emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) }
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inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) }
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emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) }
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inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) }
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emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) }
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inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) }
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emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) }
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inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) }
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emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) }
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inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) }
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emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) }
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inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) }
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emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) }
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inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) }
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emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) }
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inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) }
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inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) }
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emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) }
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inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) }
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emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) }
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inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) }
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emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) }
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inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) }
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emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) }
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inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) }
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emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) }
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inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) }
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emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) }
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inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) }
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emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) }
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inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) }
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emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) }
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inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) }
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emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) }
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inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) }
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emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) }
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inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) }
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emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) }
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inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) }
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emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) }
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inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) }
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emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) }
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inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) }
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emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) }
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inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) }
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emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) }
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inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) }
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emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) }
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inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) }
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emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) }
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inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) }
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emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) }
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inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) }
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emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) }
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inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) }
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emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) }
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inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) }
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emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) }
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inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) }
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emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) }
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inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) }
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emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) }
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inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) }
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emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) }
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inst_and_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND_IMM, dst, src, imm) }
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emit_and_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_imm_r_r_i(dst, src, imm)) }
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inst_ands_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS_IMM, dst, src, imm) }
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emit_ands_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_imm_r_r_i(dst, src, imm)) }
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inst_orr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR_IMM, dst, src, imm) }
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emit_orr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_imm_r_r_i(dst, src, imm)) }
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inst_eor_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR_IMM, dst, src, imm) }
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emit_eor_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_imm_r_r_i(dst, src, imm)) }
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inst_tst_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST_IMM, dst, imm) }
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emit_tst_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_imm_r_i(dst, imm)) }
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inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) }
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emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) }
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inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) }
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emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) }
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inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) }
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emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) }
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inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) }
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emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) }
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inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) }
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emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) }
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inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) }
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emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) }
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inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) }
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emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) }
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inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) }
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emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) }
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inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) }
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emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) }
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inst_ldr_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_PRE, dst, mem) }
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emit_ldr_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_pre_r_m(dst, mem)) }
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inst_str_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_PRE, dst, mem) }
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emit_str_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_pre_r_m(dst, mem)) }
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inst_ldr_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_POST, dst, mem) }
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emit_ldr_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_post_r_m(dst, mem)) }
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inst_str_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_POST, dst, mem) }
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emit_str_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_post_r_m(dst, mem)) }
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inst_ldrb_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_PRE, dst, mem) }
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emit_ldrb_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_pre_r_m(dst, mem)) }
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inst_strb_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_PRE, dst, mem) }
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emit_strb_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_pre_r_m(dst, mem)) }
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inst_ldrb_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_POST, dst, mem) }
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emit_ldrb_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_post_r_m(dst, mem)) }
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inst_strb_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_POST, dst, mem) }
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emit_strb_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_post_r_m(dst, mem)) }
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inst_ldrh_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_PRE, dst, mem) }
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emit_ldrh_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_pre_r_m(dst, mem)) }
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inst_strh_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_PRE, dst, mem) }
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emit_strh_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_pre_r_m(dst, mem)) }
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inst_ldrh_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_POST, dst, mem) }
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emit_ldrh_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_post_r_m(dst, mem)) }
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inst_strh_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_POST, dst, mem) }
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emit_strh_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_post_r_m(dst, mem)) }
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inst_ldr_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_REG, dst, mem) }
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emit_ldr_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_reg_r_m(dst, mem)) }
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inst_str_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_REG, dst, mem) }
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emit_str_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_reg_r_m(dst, mem)) }
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inst_ldrb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_REG, dst, mem) }
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emit_ldrb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_reg_r_m(dst, mem)) }
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inst_strb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_REG, dst, mem) }
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emit_strb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_reg_r_m(dst, mem)) }
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inst_ldrh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_REG, dst, mem) }
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emit_ldrh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_reg_r_m(dst, mem)) }
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inst_strh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_REG, dst, mem) }
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emit_strh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_reg_r_m(dst, mem)) }
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inst_ldrsb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB_REG, dst, mem) }
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emit_ldrsb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_reg_r_m(dst, mem)) }
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inst_ldrsh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH_REG, dst, mem) }
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emit_ldrsh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_reg_r_m(dst, mem)) }
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inst_ldrsw_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW_REG, dst, mem) }
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emit_ldrsw_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_reg_r_m(dst, mem)) }
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inst_ldp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_PRE, dst, src, mem) }
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emit_ldp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_pre_r_r_m(dst, src, mem)) }
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inst_stp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_PRE, dst, src, mem) }
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emit_stp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_pre_r_r_m(dst, src, mem)) }
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inst_ldp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_POST, dst, src, mem) }
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emit_ldp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_post_r_r_m(dst, src, mem)) }
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inst_stp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_POST, dst, src, mem) }
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emit_stp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_post_r_r_m(dst, src, mem)) }
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inst_ldpsw_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_PRE, dst, src, mem) }
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emit_ldpsw_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_pre_r_r_m(dst, src, mem)) }
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inst_ldpsw_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_POST, dst, src, mem) }
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emit_ldpsw_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_post_r_r_m(dst, src, mem)) }
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inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) }
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emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) }
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inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) }
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emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) }
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inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) }
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emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) }
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inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} }
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emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) }
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inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) }
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emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) }
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inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} }
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emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) }
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inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) }
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emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) }
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inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) }
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emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) }
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inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) }
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emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) }
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inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) }
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emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) }
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inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) }
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emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) }
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inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) }
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emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) }
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inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) }
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emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) }
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inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) }
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emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) }
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inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) }
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emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) }
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inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) }
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emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) }
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inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) }
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emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) }
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inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) }
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emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) }
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inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) }
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emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) }
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inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) }
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emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) }
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inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) }
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emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) }
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inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) }
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emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) }
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inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) }
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emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) }
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inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) }
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emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) }
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inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) }
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emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) }
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inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) }
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emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) }
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inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) }
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emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) }
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inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) }
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emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) }
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inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) }
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emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) }
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inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) }
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emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) }
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inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) }
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emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) }
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inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) }
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emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) }
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inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) }
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emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) }
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inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) }
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emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) }
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inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) }
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emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) }
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inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) }
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emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) }
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inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) }
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emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) }
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inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) }
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emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) }
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inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) }
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emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) }
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inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) }
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emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) }
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inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) }
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emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) }
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inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) }
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emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) }
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inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) }
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emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) }
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inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) }
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emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) }
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inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) }
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emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) }
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inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) }
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emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) }
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inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) }
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emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) }
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inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) }
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emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) }
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inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) }
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emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) }
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inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) }
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emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) }
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inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) }
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emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) }
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inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) }
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emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) }
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inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) }
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emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) }
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inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) }
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emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) }
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inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) }
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emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) }
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inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) }
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emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) }
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inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) }
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emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) }
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inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) }
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emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) }
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inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) }
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emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) }
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inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) }
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emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) }
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inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) }
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emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) }
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inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) }
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emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) }
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inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) }
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emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) }
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inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) }
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emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) }
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inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) }
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emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) }
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inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) }
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emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) }
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inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) }
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emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) }
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inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) }
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emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) }
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inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) }
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emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) }
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inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) }
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emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) }
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inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) }
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emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) }
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inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) }
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emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) }
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inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) }
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emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) }
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inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) }
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emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) }
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inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) }
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emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) }
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inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) }
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emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) }
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inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) }
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emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) }
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inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) }
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emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) }
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inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) }
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emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) }
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inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) }
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emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) }
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inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) }
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emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) }
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inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) }
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emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) }
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inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) }
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emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) }
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inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) }
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emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) }
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inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) }
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emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) }
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inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) }
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emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) }
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inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) }
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emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) }
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inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) }
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emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) }
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inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) }
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emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) }
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inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) }
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emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) }
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inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) }
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emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) }
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inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) }
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emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) }
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inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) }
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emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) }
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inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) }
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emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) }
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inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) }
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emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) }
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inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) }
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emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) }
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inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) }
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emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) }
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inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) }
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emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) }
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inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) }
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emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) }
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inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) }
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emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) }
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inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) }
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emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) }
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inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) }
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emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) }
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inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) }
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emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) }
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inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) }
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emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) }
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inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) }
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emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) }
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inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) }
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emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) }
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inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) }
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emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) }
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inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) }
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emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) }
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inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) }
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emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) }
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inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} }
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emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) }
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inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) }
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emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) }
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inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} }
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emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) }
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inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} }
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emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) }
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inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) }
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emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) }
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inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) }
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emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) }
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inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) }
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emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) }
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inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) }
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emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) }
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inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) }
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emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) }
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inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) }
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emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) }
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inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) }
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emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) }
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inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) }
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emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) }
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inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) }
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emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) }
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inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) }
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emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) }
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inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) }
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emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) }
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inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) }
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emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) }
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inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) }
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emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) }
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inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) }
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emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) }
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inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) }
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emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) }
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inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) }
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emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) }
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inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) }
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emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) }
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inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) }
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emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) }
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inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) }
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emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) }
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inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) }
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emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) }
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inst_aese_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_aese_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_r_r(dst, src)) }
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inst_aesd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_aesd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_r_r(dst, src)) }
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inst_aesmc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_aesmc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_r_r(dst, src)) }
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inst_aesimc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_aesimc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_r_r(dst, src)) }
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inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) }
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emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) }
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inst_sha1c_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha1c_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_r(dst, src, src2)) }
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inst_sha1p_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha1p_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_r(dst, src, src2)) }
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inst_sha1m_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha1m_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_r(dst, src, src2)) }
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inst_sha1su0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha1su0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_r_r_r(dst, src, src2)) }
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inst_sha1su1_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_sha1su1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_r_r(dst, src)) }
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inst_sha256h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha256h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_r(dst, src, src2)) }
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inst_sha256h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha256h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_r(dst, src, src2)) }
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inst_sha256su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_sha256su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_r_r(dst, src)) }
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inst_sha256su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sha256su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_r_r_r(dst, src, src2)) }
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inst_sha512h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} }
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emit_sha512h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_r(dst, src, src2)) }
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inst_sha512h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} }
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emit_sha512h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_r(dst, src, src2)) }
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inst_sha512su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} }
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emit_sha512su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_r_r(dst, src)) }
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inst_sha512su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} }
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emit_sha512su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_r_r_r(dst, src, src2)) }
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inst_eor3_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} }
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emit_eor3_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_r_r_r_r(dst, src, src2, src3)) }
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inst_bcax_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} }
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emit_bcax_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_r_r_r_r(dst, src, src2, src3)) }
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inst_rax1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} }
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emit_rax1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_r_r_r(dst, src, src2)) }
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inst_xar_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_xar_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_r_r_r_i(dst, src, src2, imm)) }
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inst_sm3partw1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sm3partw1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_r_r_r(dst, src, src2)) }
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inst_sm3partw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sm3partw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_r_r_r(dst, src, src2)) }
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inst_sm3ss1_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_v_4s(u8(reg_hw(src3)))}} }
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emit_sm3ss1_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_r_r_r_r(dst, src, src2, src3)) }
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inst_sm3tt1a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} }
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emit_sm3tt1a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_r_r_r(dst, src, src2)) }
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inst_sm3tt1b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} }
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emit_sm3tt1b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_r_r_r(dst, src, src2)) }
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inst_sm3tt2a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} }
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emit_sm3tt2a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_r_r_r(dst, src, src2)) }
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inst_sm3tt2b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} }
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emit_sm3tt2b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_r_r_r(dst, src, src2)) }
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inst_sm4e_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_sm4e_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_r_r(dst, src)) }
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inst_sm4ekey_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_sm4ekey_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_r_r_r(dst, src, src2)) }
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inst_pmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_pmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_r_r_r(dst, src, src2)) }
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inst_pmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_pmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_r_r_r(dst, src, src2)) }
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inst_fabs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS_H, dst, src) }
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emit_fabs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_h_r_r(dst, src)) }
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inst_fneg_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG_H, dst, src) }
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emit_fneg_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_h_r_r(dst, src)) }
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inst_fsqrt_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT_H, dst, src) }
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emit_fsqrt_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_h_r_r(dst, src)) }
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inst_fadd_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD_H, dst, src, src2) }
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emit_fadd_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_h_r_r_r(dst, src, src2)) }
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inst_fsub_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB_H, dst, src, src2) }
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emit_fsub_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_h_r_r_r(dst, src, src2)) }
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inst_fmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL_H, dst, src, src2) }
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emit_fmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_h_r_r_r(dst, src, src2)) }
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inst_fdiv_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV_H, dst, src, src2) }
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emit_fdiv_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_h_r_r_r(dst, src, src2)) }
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inst_fnmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL_H, dst, src, src2) }
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emit_fnmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_h_r_r_r(dst, src, src2)) }
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inst_fmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD_H, dst, src, src2, src3) }
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emit_fmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_h_r_r_r_r(dst, src, src2, src3)) }
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inst_fmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB_H, dst, src, src2, src3) }
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emit_fmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_h_r_r_r_r(dst, src, src2, src3)) }
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inst_fnmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD_H, dst, src, src2, src3) }
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emit_fnmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_h_r_r_r_r(dst, src, src2, src3)) }
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inst_fnmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB_H, dst, src, src2, src3) }
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emit_fnmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_h_r_r_r_r(dst, src, src2, src3)) }
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inst_fcmp_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP_H, dst, src) }
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emit_fcmp_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_h_r_r(dst, src)) }
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inst_fcmpe_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE_H, dst, src) }
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emit_fcmpe_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_h_r_r(dst, src)) }
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inst_fcsel_h_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL_H, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} }
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emit_fcsel_h_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_h_r_r_r_c(dst, src, src2, cond)) }
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inst_fmax_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX_H, dst, src, src2) }
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emit_fmax_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_h_r_r_r(dst, src, src2)) }
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inst_fmin_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN_H, dst, src, src2) }
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emit_fmin_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_h_r_r_r(dst, src, src2)) }
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inst_fmaxnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM_H, dst, src, src2) }
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emit_fmaxnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_h_r_r_r(dst, src, src2)) }
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inst_fminnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM_H, dst, src, src2) }
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emit_fminnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_h_r_r_r(dst, src, src2)) }
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inst_fcvt_h_s_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_S, dst, src) }
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emit_fcvt_h_s_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_s_r_r(dst, src)) }
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inst_fcvt_h_d_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_D, dst, src) }
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emit_fcvt_h_d_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_d_r_r(dst, src)) }
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inst_fcvt_s_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_S_H, dst, src) }
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emit_fcvt_s_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_s_h_r_r(dst, src)) }
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inst_fcvt_d_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_D_H, dst, src) }
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emit_fcvt_d_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_d_h_r_r(dst, src)) }
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inst_fmov_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_H, dst, src) }
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emit_fmov_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_h_r_r(dst, src)) }
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inst_scvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF_H, dst, src) }
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emit_scvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_h_r_r(dst, src)) }
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inst_ucvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF_H, dst, src) }
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emit_ucvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_h_r_r(dst, src)) }
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inst_fcvtzs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS_H, dst, src) }
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emit_fcvtzs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_h_r_r(dst, src)) }
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inst_fcvtzu_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU_H, dst, src) }
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emit_fcvtzu_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_h_r_r(dst, src)) }
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inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) }
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emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) }
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inst_bfdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_bfdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_r_r_r(dst, src, src2)) }
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inst_bfmmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_bfmmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_r_r_r(dst, src, src2)) }
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inst_bfmlalb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_bfmlalb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_r_r_r(dst, src, src2)) }
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inst_bfmlalt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_bfmlalt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_r_r_r(dst, src, src2)) }
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inst_bfcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_bfcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_r_r(dst, src)) }
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inst_bfcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_bfcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_r_r(dst, src)) }
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inst_add_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_add_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v_r_r_r(dst, src, src2)) }
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inst_sub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_sub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v_r_r_r(dst, src, src2)) }
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inst_mul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_mul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v_r_r_r(dst, src, src2)) }
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inst_mla_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_mla_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v_r_r_r(dst, src, src2)) }
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inst_mls_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_mls_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v_r_r_r(dst, src, src2)) }
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inst_neg_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_neg_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v_r_r(dst, src)) }
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inst_abs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_abs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v_r_r(dst, src)) }
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inst_shadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_shadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_r_r_r(dst, src, src2)) }
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inst_uhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_r_r_r(dst, src, src2)) }
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inst_shsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_shsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_r_r_r(dst, src, src2)) }
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inst_uhsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uhsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_r_r_r(dst, src, src2)) }
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inst_srhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_srhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_r_r_r(dst, src, src2)) }
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inst_urhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_urhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_r_r_r(dst, src, src2)) }
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inst_sqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_r_r_r(dst, src, src2)) }
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inst_uqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_r_r_r(dst, src, src2)) }
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inst_sqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_r_r_r(dst, src, src2)) }
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inst_uqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_r_r_r(dst, src, src2)) }
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inst_smax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_r_r_r(dst, src, src2)) }
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inst_umax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_r_r_r(dst, src, src2)) }
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inst_smin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_r_r_r(dst, src, src2)) }
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inst_umin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_r_r_r(dst, src, src2)) }
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inst_sabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_r_r_r(dst, src, src2)) }
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inst_uabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_r_r_r(dst, src, src2)) }
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inst_saba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_saba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_r_r_r(dst, src, src2)) }
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inst_uaba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uaba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_r_r_r(dst, src, src2)) }
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inst_addp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_addp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v_r_r_r(dst, src, src2)) }
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inst_addv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_addv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_r(dst, src)) }
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inst_saddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_saddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_r_r(dst, src)) }
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inst_uaddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_uaddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_r_r(dst, src)) }
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inst_sadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_sadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_r_r(dst, src)) }
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inst_uadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_uadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_r_r(dst, src)) }
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inst_saddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_saddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_r(dst, src)) }
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inst_uaddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_uaddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_r(dst, src)) }
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inst_smaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_smaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_r(dst, src)) }
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inst_umaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_umaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_r(dst, src)) }
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inst_sminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_sminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_r(dst, src)) }
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inst_uminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_uminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_r(dst, src)) }
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inst_smaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_r_r_r(dst, src, src2)) }
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inst_umaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_r_r_r(dst, src, src2)) }
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inst_sminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_r_r_r(dst, src, src2)) }
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inst_uminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_r_r_r(dst, src, src2)) }
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inst_saddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_saddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_r_r_r(dst, src, src2)) }
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inst_saddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_saddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_r_r_r(dst, src, src2)) }
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inst_uaddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uaddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_r_r_r(dst, src, src2)) }
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inst_uaddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_uaddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_r_r_r(dst, src, src2)) }
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inst_ssubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_ssubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_r_r_r(dst, src, src2)) }
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inst_ssubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_ssubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_r_r_r(dst, src, src2)) }
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inst_usubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_usubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_r_r_r(dst, src, src2)) }
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inst_usubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_usubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_r_r_r(dst, src, src2)) }
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inst_saddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_saddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_r_r_r(dst, src, src2)) }
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inst_saddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_saddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_r_r_r(dst, src, src2)) }
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inst_uaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_r_r_r(dst, src, src2)) }
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inst_uaddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_uaddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_r_r_r(dst, src, src2)) }
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inst_ssubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_ssubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_r_r_r(dst, src, src2)) }
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inst_ssubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_ssubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_r_r_r(dst, src, src2)) }
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inst_usubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_usubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_r_r_r(dst, src, src2)) }
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inst_usubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_usubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_r_r_r(dst, src, src2)) }
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inst_raddhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_raddhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_r_r_r(dst, src, src2)) }
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inst_raddhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_raddhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_r_r_r(dst, src, src2)) }
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inst_rsubhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_rsubhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_r_r_r(dst, src, src2)) }
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inst_rsubhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_rsubhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_r_r_r(dst, src, src2)) }
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inst_addhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_addhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_r_r_r(dst, src, src2)) }
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inst_addhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_addhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_r_r_r(dst, src, src2)) }
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inst_subhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_subhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_r_r_r(dst, src, src2)) }
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inst_subhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_subhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_r_r_r(dst, src, src2)) }
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inst_xtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_xtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_r_r(dst, src)) }
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inst_xtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_xtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_r_r(dst, src)) }
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inst_sqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_sqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_r_r(dst, src)) }
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inst_sqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_sqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_r_r(dst, src)) }
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inst_uqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_uqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_r_r(dst, src)) }
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inst_uqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_uqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_r_r(dst, src)) }
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inst_sqxtun_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_sqxtun_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_r_r(dst, src)) }
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inst_sqxtun2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_sqxtun2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_r_r(dst, src)) }
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inst_smull_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smull_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v_r_r_r(dst, src, src2)) }
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inst_smull2_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_smull2_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v_r_r_r(dst, src, src2)) }
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inst_umull_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umull_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v_r_r_r(dst, src, src2)) }
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inst_umull2_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_umull2_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v_r_r_r(dst, src, src2)) }
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inst_smlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_r_r_r(dst, src, src2)) }
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inst_smlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_smlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_r_r_r(dst, src, src2)) }
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inst_umlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_r_r_r(dst, src, src2)) }
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inst_umlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_umlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_r_r_r(dst, src, src2)) }
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inst_smlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_smlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_r_r_r(dst, src, src2)) }
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inst_smlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_smlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_r_r_r(dst, src, src2)) }
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inst_umlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_umlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_r_r_r(dst, src, src2)) }
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inst_umlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_umlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_r_r_r(dst, src, src2)) }
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inst_sqdmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
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emit_sqdmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_r_r_r(dst, src, src2)) }
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inst_sqdmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_sqdmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_r_r_r(dst, src, src2)) }
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inst_sqdmlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
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emit_sqdmlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_r_r_r(dst, src, src2)) }
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inst_sqdmlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_sqdmlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_r_r_r(dst, src, src2)) }
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inst_sqdmlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
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emit_sqdmlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_r_r_r(dst, src, src2)) }
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inst_sqdmlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} }
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emit_sqdmlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_r_r_r(dst, src, src2)) }
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inst_sqdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
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emit_sqdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_r_r_r(dst, src, src2)) }
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inst_sqrdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
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emit_sqrdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_r_r_r(dst, src, src2)) }
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inst_sdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_r_r_r(dst, src, src2)) }
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inst_udot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_udot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_r_r_r(dst, src, src2)) }
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inst_usdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_usdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_r_r_r(dst, src, src2)) }
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inst_fadd_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fadd_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v_r_r_r(dst, src, src2)) }
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inst_fsub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fsub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v_r_r_r(dst, src, src2)) }
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inst_fmul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v_r_r_r(dst, src, src2)) }
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inst_fdiv_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fdiv_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v_r_r_r(dst, src, src2)) }
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inst_fneg_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fneg_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v_r_r(dst, src)) }
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inst_fabs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fabs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v_r_r(dst, src)) }
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inst_fsqrt_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fsqrt_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v_r_r(dst, src)) }
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inst_fmla_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_fmla_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v_r_r_r(dst, src, src2)) }
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inst_fmls_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} }
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emit_fmls_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v_r_r_r(dst, src, src2)) }
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inst_fmulx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmulx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_r_r_r(dst, src, src2)) }
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inst_fmax_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmax_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v_r_r_r(dst, src, src2)) }
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inst_fmin_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmin_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v_r_r_r(dst, src, src2)) }
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inst_fmaxnm_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmaxnm_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v_r_r_r(dst, src, src2)) }
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inst_fminnm_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fminnm_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v_r_r_r(dst, src, src2)) }
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inst_fmaxp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmaxp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v_r_r_r(dst, src, src2)) }
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inst_fminp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fminp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v_r_r_r(dst, src, src2)) }
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inst_fmaxnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fmaxnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_r_r_r(dst, src, src2)) }
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inst_fminnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fminnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_r_r_r(dst, src, src2)) }
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inst_fmaxv_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV_V, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fmaxv_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_v_r_r(dst, src)) }
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inst_fminv_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV_V, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fminv_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_v_r_r(dst, src)) }
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inst_fmaxnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fmaxnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_r(dst, src)) }
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inst_fminnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fminnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_r(dst, src)) }
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inst_frecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_r_r(dst, src)) }
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inst_frsqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frsqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_r_r(dst, src)) }
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inst_frecps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_frecps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_r_r_r(dst, src, src2)) }
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inst_frsqrts_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_frsqrts_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_r_r_r(dst, src, src2)) }
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inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) }
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emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) }
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inst_faddp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_faddp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v_r_r_r(dst, src, src2)) }
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inst_frinta_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frinta_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v_r_r(dst, src)) }
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inst_frinti_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frinti_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v_r_r(dst, src)) }
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inst_frintm_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frintm_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v_r_r(dst, src)) }
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inst_frintn_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frintn_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v_r_r(dst, src)) }
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inst_frintp_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frintp_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v_r_r(dst, src)) }
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inst_frintx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frintx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v_r_r(dst, src)) }
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inst_frintz_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_frintz_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v_r_r(dst, src)) }
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inst_scvtf_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_scvtf_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v_r_r(dst, src)) }
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inst_ucvtf_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_ucvtf_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v_r_r(dst, src)) }
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inst_fcvtas_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtas_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v_r_r(dst, src)) }
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inst_fcvtau_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtau_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v_r_r(dst, src)) }
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inst_fcvtms_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtms_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v_r_r(dst, src)) }
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inst_fcvtmu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtmu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v_r_r(dst, src)) }
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inst_fcvtns_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtns_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v_r_r(dst, src)) }
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inst_fcvtnu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtnu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v_r_r(dst, src)) }
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inst_fcvtps_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtps_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v_r_r(dst, src)) }
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inst_fcvtpu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtpu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v_r_r(dst, src)) }
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inst_fcvtzs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtzs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v_r_r(dst, src)) }
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inst_fcvtzu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtzu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v_r_r(dst, src)) }
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inst_fcvtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_r_r(dst, src)) }
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inst_fcvtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_r_r(dst, src)) }
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inst_fcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_r_r(dst, src)) }
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inst_fcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_r_r(dst, src)) }
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inst_fcvtxn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtxn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_r_r(dst, src)) }
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inst_fcvtxn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} }
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emit_fcvtxn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_r_r(dst, src)) }
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inst_fcmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fcmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_r_r_r(dst, src, src2)) }
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inst_fcmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fcmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_r_r_r(dst, src, src2)) }
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inst_fcmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_fcmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_r_r_r(dst, src, src2)) }
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inst_fcmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_r_r(dst, src)) }
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inst_fcmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_fcmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_r_r(dst, src)) }
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inst_facge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_facge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_r_r_r(dst, src, src2)) }
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inst_facgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} }
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emit_facgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_r_r_r(dst, src, src2)) }
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inst_cmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_cmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_r_r_r(dst, src, src2)) }
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inst_cmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_cmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_r_r_r(dst, src, src2)) }
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inst_cmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_cmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_r_r_r(dst, src, src2)) }
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inst_cmhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_cmhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_r_r_r(dst, src, src2)) }
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inst_cmhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_cmhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_r_r_r(dst, src, src2)) }
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inst_cmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_cmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_r_r(dst, src)) }
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inst_cmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_cmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_r_r(dst, src)) }
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inst_cmtst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_cmtst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_r_r_r(dst, src, src2)) }
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inst_and_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_and_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v_r_r_r(dst, src, src2)) }
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inst_orr_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_orr_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v_r_r_r(dst, src, src2)) }
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inst_eor_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_eor_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v_r_r_r(dst, src, src2)) }
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inst_bic_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_bic_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v_r_r_r(dst, src, src2)) }
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inst_orn_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_orn_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v_r_r_r(dst, src, src2)) }
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inst_mvn_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_mvn_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v_r_r(dst, src)) }
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inst_bit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_bit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_r_r_r(dst, src, src2)) }
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inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) }
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inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
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emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) }
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inst_shl_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_shl_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v_r_r_i(dst, src, imm)) }
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inst_sqshl_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshl_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v_r_r_i(dst, src, imm)) }
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inst_sqshlu_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshlu_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_r_r_i(dst, src, imm)) }
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inst_srshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_srshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_r_r_r(dst, src, src2)) }
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inst_urshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_urshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_r_r_r(dst, src, src2)) }
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inst_sshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_r_r_i(dst, src, imm)) }
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inst_ushr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_ushr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_r_r_i(dst, src, imm)) }
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inst_ssra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_ssra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_r_r_i(dst, src, imm)) }
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inst_usra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_usra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_r_r_i(dst, src, imm)) }
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inst_srshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_srshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_r_r_i(dst, src, imm)) }
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inst_urshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_urshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_r_r_i(dst, src, imm)) }
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inst_srsra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_srsra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_r_r_i(dst, src, imm)) }
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inst_ursra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_ursra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_r_r_i(dst, src, imm)) }
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inst_sshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_sshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_r_r_r(dst, src, src2)) }
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inst_ushl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_ushl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_r_r_r(dst, src, src2)) }
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inst_sli_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sli_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_r_r_i(dst, src, imm)) }
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inst_sri_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sri_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_r_r_i(dst, src, imm)) }
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inst_sshll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sshll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_r_r_i(dst, src, imm)) }
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inst_sshll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sshll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_r_r_i(dst, src, imm)) }
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inst_ushll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_ushll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_r_r_i(dst, src, imm)) }
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inst_ushll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_ushll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_r_r_i(dst, src, imm)) }
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inst_sxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_sxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_r_r(dst, src)) }
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inst_sxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_sxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_r_r(dst, src)) }
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inst_uxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_uxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_r_r(dst, src)) }
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inst_uxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} }
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emit_uxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_r_r(dst, src)) }
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inst_shrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_shrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_r_r_i(dst, src, imm)) }
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inst_shrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_shrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_r_r_i(dst, src, imm)) }
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inst_rshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_rshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_r_r_i(dst, src, imm)) }
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inst_rshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_rshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_r_r_i(dst, src, imm)) }
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inst_sqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_r_r_i(dst, src, imm)) }
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inst_sqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_r_r_i(dst, src, imm)) }
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inst_uqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_uqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_r_r_i(dst, src, imm)) }
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inst_uqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_uqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_r_r_i(dst, src, imm)) }
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inst_sqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_r_r_i(dst, src, imm)) }
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inst_sqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_r_r_i(dst, src, imm)) }
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inst_uqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_uqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_r_r_i(dst, src, imm)) }
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inst_uqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_uqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_r_r_i(dst, src, imm)) }
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inst_sqshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_r_r_i(dst, src, imm)) }
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inst_sqshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_r_r_i(dst, src, imm)) }
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inst_sqrshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqrshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_r_r_i(dst, src, imm)) }
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inst_sqrshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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emit_sqrshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_r_r_i(dst, src, imm)) }
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inst_dup_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_elem_b(u8(reg_hw(src))), op_imm(imm, 4), {}}} }
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inst_dup_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_reg(src), {}, {}}} }
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emit_dup_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v_r_r_i(dst, src, imm)) }
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emit_dup_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v_r_r(dst, src)) }
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inst_ins_r_i_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_v_elem_b(u8(reg_hw(src))), op_imm(imm2, 4)}} }
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inst_ins_r_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_reg(src), {}}} }
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emit_ins_r_i_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_r_i_r_i(dst, imm, src, imm2)) }
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emit_ins_r_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_r_i_r(dst, imm, src)) }
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inst_mov_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_mov_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v_r_r(dst, src)) }
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inst_ext_v_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT_V, operand_count = 4, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), op_imm(imm, 4)}} }
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emit_ext_v_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v_r_r_r_i(dst, src, src2, imm)) }
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inst_tbl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_tbl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_r_r_r(dst, src, src2)) }
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inst_tbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_tbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_r_r_r(dst, src, src2)) }
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inst_zip1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_zip1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_r_r_r(dst, src, src2)) }
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inst_zip2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_zip2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_r_r_r(dst, src, src2)) }
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inst_uzp1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uzp1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_r_r_r(dst, src, src2)) }
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inst_uzp2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_uzp2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_r_r_r(dst, src, src2)) }
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inst_trn1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_trn1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_r_r_r(dst, src, src2)) }
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inst_trn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
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emit_trn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_r_r_r(dst, src, src2)) }
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inst_not_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_not_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_r_r(dst, src)) }
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inst_rbit_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_rbit_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v_r_r(dst, src)) }
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inst_rev16_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_rev16_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v_r_r(dst, src)) }
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inst_rev32_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_rev32_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v_r_r(dst, src)) }
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inst_rev64_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_rev64_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_r_r(dst, src)) }
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inst_cls_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_cls_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v_r_r(dst, src)) }
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inst_clz_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_clz_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v_r_r(dst, src)) }
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inst_cnt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_cnt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_r_r(dst, src)) }
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inst_urecpe_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_urecpe_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v_r_r(dst, src)) }
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inst_ursqrte_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} }
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emit_ursqrte_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v_r_r(dst, src)) }
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inst_movi_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} }
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emit_movi_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_r_i(dst, imm)) }
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inst_mvni_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} }
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emit_mvni_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_r_i(dst, imm)) }
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inst_fmov_v_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV_V_IMM, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} }
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emit_fmov_v_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v_imm_r_i(dst, imm)) }
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inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) }
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inst_ld2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_r_m(dst, mem)) }
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inst_ld3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_r_m(dst, mem)) }
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inst_ld4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_r_m(dst, mem)) }
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inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_st1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_r_m(dst, mem)) }
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inst_st2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_st2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_r_m(dst, mem)) }
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inst_st3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_st3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_r_m(dst, mem)) }
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inst_st4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_st4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_r_m(dst, mem)) }
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inst_ld1r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld1r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_r_m(dst, mem)) }
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inst_ld2r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld2r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_r_m(dst, mem)) }
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inst_ld3r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld3r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_r_m(dst, mem)) }
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inst_ld4r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} }
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emit_ld4r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_r_m(dst, mem)) }
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inst_ld1_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_ld1_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_lane_r_i_m(dst, imm, mem)) }
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inst_ld2_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_ld2_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_lane_r_i_m(dst, imm, mem)) }
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inst_ld3_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_ld3_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_lane_r_i_m(dst, imm, mem)) }
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inst_ld4_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_ld4_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_lane_r_i_m(dst, imm, mem)) }
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inst_st1_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_st1_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_lane_r_i_m(dst, imm, mem)) }
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inst_st2_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_st2_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_lane_r_i_m(dst, imm, mem)) }
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inst_st3_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_st3_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_lane_r_i_m(dst, imm, mem)) }
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inst_st4_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} }
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emit_st4_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_lane_r_i_m(dst, imm, mem)) }
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inst_ldr_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_V, dst, mem) }
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emit_ldr_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_v_r_m(dst, mem)) }
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inst_str_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_V, dst, mem) }
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emit_str_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_v_r_m(dst, mem)) }
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inst_ldp_v_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_V, dst, src, mem) }
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emit_ldp_v_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_v_r_r_m(dst, src, mem)) }
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inst_stp_v_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_V, dst, src, mem) }
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emit_stp_v_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_v_r_r_m(dst, src, mem)) }
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inst_ldur_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR_V, dst, mem) }
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emit_ldur_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_v_r_m(dst, mem)) }
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inst_stur_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR_V, dst, mem) }
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emit_stur_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_v_r_m(dst, mem)) }
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inst_sve_add_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_add_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_add_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_sub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_sub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sub_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_sqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_sqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqadd_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_uqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_uqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqadd_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_sqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_sqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqsub_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_uqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_uqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqsub_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_add_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_add_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_add_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_sub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_sub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sub_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_subr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUBR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_subr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_subr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_mul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MUL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_mul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_mul_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_smulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_smulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_umulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_umulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_sdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} }
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emit_sve_sdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_udiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} }
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emit_sve_udiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_udiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_smax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_smax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smax_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_umax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_umax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umax_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_smin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_smin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smin_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_umin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_umin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umin_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_sabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_sabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_uabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_uabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_uabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_and_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_and_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_orr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_orr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_eor_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_eor_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bic_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_bic_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_asr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_asr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lsl_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lsl_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsl_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lsr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lsr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_asrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_asrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lslr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSLR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lslr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lslr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lsrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lsrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_abs_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ABS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_abs_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_abs_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_neg_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NEG_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_neg_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_neg_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_cls_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_cls_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cls_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_clz_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLZ_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_clz_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_clz_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_cnt_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CNT_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_cnt_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cnt_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_mov_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_mov_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_mov_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_fadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_fadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fadd_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_fsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_fsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsub_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_fmul_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_fmul_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fmul_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecps_z_z_z(rz, rz2, rz3)) }
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inst_sve_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frsqrts_z_z_z(rz, rz2, rz3)) }
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inst_sve_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_ftsmul_z_z_z(rz, rz2, rz3)) }
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inst_sve_fadd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fadd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fadd_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fsub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fsub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsub_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fsubr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUBR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fsubr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsubr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmul_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIV_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fdivr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIVR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fdivr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdivr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAX_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmax_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMIN_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmin_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAXNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmaxnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fminnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMINNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fminnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fminnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fabs_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FABS_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fabs_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fabs_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_fneg_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNEG_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fneg_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fneg_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_fsqrt_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSQRT_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fsqrt_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsqrt_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_frecpx_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPX_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frecpx_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecpx_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintn_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintp_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintm_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintz_z_p_z(rz, rz2, rz3)) }
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inst_sve_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinta_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintx_z_p_z(rz, rz2, rz3)) }
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inst_sve_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinti_z_p_z(rz, rz2, rz3)) }
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inst_sve_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmla_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmls_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_and_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_and_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_bic_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_bic_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_orr_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_orr_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_eor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_eor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nand_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NAND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nand_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nand_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nor_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_orn_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORN_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_orn_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orn_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_sel_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SEL_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_sel_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sel_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_ands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_ands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_ands_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_bics_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BICS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_bics_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bics_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_orrs_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORRS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_orrs_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orrs_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_eors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_eors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eors_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nands_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nors_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_orns_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORNS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_orns_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orns_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_not_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NOT_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_not_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_not_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_mov_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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inst_sve_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} }
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emit_sve_mov_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_mov_p_p_p_p(rz, rz2, rz3)) }
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emit_sve_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_mov_p_p_p(rz, rz2)) }
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inst_sve_movs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOVS_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_movs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_movs_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} }
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emit_sve_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrue_p_i(rz, imm)) }
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inst_sve_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} }
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emit_sve_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrues_p_i(rz, imm)) }
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inst_sve_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} }
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emit_sve_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_pfalse_p(rz)) }
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inst_sve_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pfirst_p_p_p(rz, rz2, rz3)) }
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inst_sve_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pnext_p_p_p(rz, rz2, rz3)) }
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inst_sve_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brka_p_p_p(rz, rz2, rz3)) }
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inst_sve_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkb_p_p_p(rz, rz2, rz3)) }
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inst_sve_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkas_p_p_p(rz, rz2, rz3)) }
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inst_sve_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkbs_p_p_p(rz, rz2, rz3)) }
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inst_sve_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkn_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} }
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emit_sve_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_rdffr_p(rz)) }
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inst_sve_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} }
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emit_sve_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_wrffr_p(rz)) }
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inst_sve_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SVE_SETFFR) }
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emit_sve_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sve_setffr_none()) }
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inst_sve_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmple_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmle_p_p_z(rz, rz2, rz3)) }
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inst_sve_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmlt_p_p_z(rz, rz2, rz3)) }
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inst_sve_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_dup_z_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_DUP_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} }
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emit_sve_dup_z_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_dup_z_z_r(rz, src)) }
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inst_sve_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} }
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emit_sve_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_insr_z_r(rz, src)) }
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inst_sve_rev_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} }
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emit_sve_rev_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_z_z_z(rz, rz2)) }
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inst_sve_rev_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} }
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emit_sve_rev_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_p_p_p(rz, rz2)) }
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inst_sve_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl_z_z_z(rz, rz2, rz3)) }
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inst_sve_zip1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_zip1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_zip2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_zip2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_uzp1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_uzp1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_uzp2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_uzp2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_trn1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_trn1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_trn2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_trn2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_z_z_z_z(rz, rz2, rz3)) }
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inst_sve_zip1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_zip1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_zip2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_zip2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_uzp1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_uzp1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_uzp2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_uzp2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_trn1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_trn1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_trn2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
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emit_sve_trn2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_p_p_p_p(rz, rz2, rz3)) }
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inst_sve_cpy_z_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_CPY_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} }
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emit_sve_cpy_z_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_sve_cpy_z_z_p_r(rz, rz2, src)) }
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inst_sve_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} }
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emit_sve_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_compact_z_p_z(rz, rz2, rz3)) }
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inst_sve_ext_z_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_EXT_Z, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} }
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emit_sve_ext_z_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_ext_z_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_z_p_m(rz, rz2, mem)) }
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inst_sve_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_z_p_m(rz, rz2, mem)) }
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inst_sve_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_z_p_m(rz, rz2, mem)) }
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inst_sve_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_z_p_m(rz, rz2, mem)) }
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inst_sve_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_z_p_m(rz, rz2, mem)) }
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inst_sve_ldr_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} }
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emit_sve_ldr_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_z_z_m(rz, mem)) }
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inst_sve_str_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} }
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emit_sve_str_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_z_z_m(rz, mem)) }
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inst_sve_ldr_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} }
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emit_sve_ldr_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_p_p_m(rz, mem)) }
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inst_sve_str_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} }
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emit_sve_str_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_p_p_m(rz, mem)) }
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inst_sve_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1b_z_p_m(rz, rz2, mem)) }
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inst_sve_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1h_z_p_m(rz, rz2, mem)) }
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inst_sve_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1w_z_p_m(rz, rz2, mem)) }
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inst_sve_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1d_z_p_m(rz, rz2, mem)) }
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inst_sve_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilege_p_r_r(rz, src, src2)) }
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inst_sve_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilegt_p_r_r(rz, src, src2)) }
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inst_sve_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilele_p_r_r(rz, src, src2)) }
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inst_sve_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelt_p_r_r(rz, src, src2)) }
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inst_sve_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehi_p_r_r(rz, src, src2)) }
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inst_sve_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehs_p_r_r(rz, src, src2)) }
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inst_sve_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelo_p_r_r(rz, src, src2)) }
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inst_sve_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} }
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emit_sve_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilels_p_r_r(rz, src, src2)) }
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inst_sve_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlah_z_z_z(rz, rz2, rz3)) }
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inst_sve_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlsh_z_z_z(rz, rz2, rz3)) }
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inst_sve_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclb_z_z_z(rz, rz2, rz3)) }
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inst_sve_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclt_z_z_z(rz, rz2, rz3)) }
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inst_sve_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclb_z_z_z(rz, rz2, rz3)) }
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inst_sve_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclt_z_z_z(rz, rz2, rz3)) }
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inst_sve_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl2_z_z_z(rz, rz2, rz3)) }
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inst_sve_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbx_z_z_z(rz, rz2, rz3)) }
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inst_sve_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} }
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emit_sve_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aese_z_z(rz, rz2)) }
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inst_sve_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} }
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emit_sve_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aesd_z_z(rz, rz2)) }
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inst_sve_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} }
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emit_sve_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesmc_z(rz)) }
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inst_sve_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} }
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emit_sve_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesimc_z(rz)) }
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inst_sve_bcax_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BCAX_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_bcax_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bcax_z_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_xar_z_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_XAR_Z, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} }
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emit_sve_xar_z_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_xar_z_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_eor3_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR3_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_eor3_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor3_z_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_match_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} }
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emit_sve_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_histseg_z_z_z(rz, rz2, rz3)) }
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inst_sme_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTART) }
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emit_sme_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstart_none()) }
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inst_sme_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTOP) }
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emit_sme_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstop_none()) }
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inst_sme_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.SME_RDSVL, dst, imm) }
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emit_sme_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sme_rdsvl_r_i(dst, imm)) }
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inst_sme_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} }
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emit_sme_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_addha_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} }
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emit_sme_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_addva_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SME_ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} }
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emit_sme_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sme_zero_i(imm)) }
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inst_sme_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} }
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emit_sme_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} }
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emit_sme_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmops_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} }
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emit_sme_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} }
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emit_sme_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smops_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umops_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} }
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emit_sme_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) }
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inst_sme_ldr_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LDR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} }
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emit_sme_ldr_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_ldr_za_i_m(imm, mem)) }
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inst_sme_str_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_STR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} }
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emit_sme_str_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_str_za_i_m(imm, mem)) }
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inst_sve_fmla_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} }
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emit_sve_fmla_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_h_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_fmla_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} }
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emit_sve_fmla_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_s_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_fmla_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} }
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emit_sve_fmla_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_d_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_fmls_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} }
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emit_sve_fmls_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_h_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_fmls_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} }
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emit_sve_fmls_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_s_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_fmls_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} }
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emit_sve_fmls_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_d_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_ld1b_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1b_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_s_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1b_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1b_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1h_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1h_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_s_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1h_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1h_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1w_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1w_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_s_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1w_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1w_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1d_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1d_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sb_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sb_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_s_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sb_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sb_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sh_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sh_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_s_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sh_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sh_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_ld1sw_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ld1sw_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_gather_d_z_p_m(rz, rz2, mem)) }
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inst_sve_st1b_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1b_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_s_z_p_m(rz, rz2, mem)) }
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inst_sve_st1b_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1b_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_d_z_p_m(rz, rz2, mem)) }
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inst_sve_st1h_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1h_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_s_z_p_m(rz, rz2, mem)) }
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inst_sve_st1h_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1h_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_d_z_p_m(rz, rz2, mem)) }
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inst_sve_st1w_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1w_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_s_z_p_m(rz, rz2, mem)) }
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inst_sve_st1w_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1w_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_d_z_p_m(rz, rz2, mem)) }
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inst_sve_st1d_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_st1d_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_scatter_d_z_p_m(rz, rz2, mem)) }
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inst_sme_ld1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_ld1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1b_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_ld1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_ld1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1h_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_ld1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_ld1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1w_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_ld1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_ld1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1d_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_ld1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_ld1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1q_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_st1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_st1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1b_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_st1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_st1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1h_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_st1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_st1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1w_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_st1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_st1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1d_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_st1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sme_st1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1q_tile_i_p_m(imm, rz1, mem)) }
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inst_sme_mova_z_from_tile_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME_MOVA_Z_FROM_TILE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} }
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emit_sme_mova_z_from_tile_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_sme_mova_z_from_tile_z_p_i(rz, rz2, imm)) }
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inst_sme_mova_tile_from_z_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME_MOVA_TILE_FROM_Z, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} }
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emit_sme_mova_tile_from_z_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_sme_mova_tile_from_z_i_p_z(imm, rz1, rz2)) }
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inst_fcmla_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcmla_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4h_r_r_r_i(dst, src, src2, imm)) }
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inst_fcmla_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcmla_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_8h_r_r_r_i(dst, src, src2, imm)) }
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inst_fcmla_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcmla_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4s_r_r_r_i(dst, src, src2, imm)) }
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inst_fcmla_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcmla_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_2d_r_r_r_i(dst, src, src2, imm)) }
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inst_fcadd_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcadd_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4h_r_r_r_i(dst, src, src2, imm)) }
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inst_fcadd_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcadd_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_8h_r_r_r_i(dst, src, src2, imm)) }
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inst_fcadd_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcadd_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4s_r_r_r_i(dst, src, src2, imm)) }
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inst_fcadd_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} }
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emit_fcadd_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_2d_r_r_r_i(dst, src, src2, imm)) }
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inst_sve_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sve_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfb_i_p_m(imm, rz1, mem)) }
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inst_sve_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sve_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfh_i_p_m(imm, rz1, mem)) }
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inst_sve_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sve_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfw_i_p_m(imm, rz1, mem)) }
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inst_sve_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} }
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emit_sve_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfd_i_p_m(imm, rz1, mem)) }
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inst_sve_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1b_z_p_m(rz, rz2, mem)) }
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inst_sve_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1h_z_p_m(rz, rz2, mem)) }
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inst_sve_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1w_z_p_m(rz, rz2, mem)) }
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inst_sve_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1d_z_p_m(rz, rz2, mem)) }
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inst_sve_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1b_z_p_m(rz, rz2, mem)) }
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inst_sve_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1h_z_p_m(rz, rz2, mem)) }
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inst_sve_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1w_z_p_m(rz, rz2, mem)) }
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inst_sve_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sve_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1d_z_p_m(rz, rz2, mem)) }
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inst_sve_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} }
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emit_sve_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_ext_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sve_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_splice_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_index_ii_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_II, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} }
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emit_sve_index_ii_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sve_index_ii_z_i_i(rz, imm, imm2)) }
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inst_sve_index_ir_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_IR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} }
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emit_sve_index_ir_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_sve_index_ir_z_i_r(rz, imm, src)) }
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inst_sve_index_ri_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RI, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} }
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emit_sve_index_ri_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_sve_index_ri_z_r_i(rz, src, imm)) }
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inst_sve_index_rr_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} }
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emit_sve_index_rr_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_index_rr_z_r_r(rz, src, src2)) }
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inst_sve_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
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emit_sve_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_pmul_vec_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMUL_VEC, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sve_pmul_vec_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmul_vec_z_z_z(rz, rz2, rz3)) }
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inst_sve_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullb_z_z_z(rz, rz2, rz3)) }
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inst_sve_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} }
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emit_sve_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullt_z_z_z(rz, rz2, rz3)) }
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inst_sve_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} }
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emit_sve_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvt_z_p_z(rz, rz2, rz3)) }
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inst_sve_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} }
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emit_sve_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvtnt_z_p_z(rz, rz2, rz3)) }
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inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) }
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emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) }
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inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) }
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emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) }
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inst_ldraa_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA_PRE, dst, mem) }
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emit_ldraa_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_pre_r_m(dst, mem)) }
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inst_ldrab_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB_PRE, dst, mem) }
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emit_ldrab_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_pre_r_m(dst, mem)) }
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inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) }
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emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) }
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inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) }
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emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) }
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inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} }
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emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) }
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inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) }
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emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) }
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inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) }
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emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) }
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inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) }
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emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) }
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inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} }
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emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) }
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inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) }
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emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) }
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inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) }
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emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) }
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inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) }
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emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) }
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inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) }
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emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) }
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inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) }
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emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) }
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inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) }
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emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) }
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inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) }
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emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) }
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inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) }
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emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) }
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inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) }
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emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) }
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inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) }
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emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) }
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inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) }
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emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) }
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inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) }
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emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) }
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inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) }
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emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) }
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inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) }
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emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) }
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inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) }
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emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) }
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inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) }
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emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) }
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inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) }
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emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) }
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inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) }
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emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) }
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inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) }
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emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) }
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inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) }
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emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) }
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inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) }
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emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) }
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inst_sve_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) }
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emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) }
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inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) }
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emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) }
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inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) }
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emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) }
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inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) }
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emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) }
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inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) }
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emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) }
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inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) }
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emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) }
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inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) }
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emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) }
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inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) }
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emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) }
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inst_mov_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_mov_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v_alias_r_r(dst, src)) }
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inst_not_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
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emit_not_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_alias_r_r(dst, src)) }
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inst_lsl_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL_IMM, dst, src, imm) }
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emit_lsl_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_imm_r_r_i(dst, src, imm)) }
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inst_lsr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR_IMM, dst, src, imm) }
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emit_lsr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_imm_r_r_i(dst, src, imm)) }
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inst_asr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR_IMM, dst, src, imm) }
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emit_asr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_imm_r_r_i(dst, src, imm)) }
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inst_ror_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR_IMM, dst, src, imm) }
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emit_ror_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_imm_r_r_i(dst, src, imm)) }
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inst_sve_bfadd_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_bfadd_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfadd_unpred_z_z_z(rz, rz2, rz3)) }
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inst_sve_bfsub_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_bfsub_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfsub_unpred_z_z_z(rz, rz2, rz3)) }
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inst_sve_bfmul_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_bfmul_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfmul_unpred_z_z_z(rz, rz2, rz3)) }
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inst_sve_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} }
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emit_sve_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfclamp_z_z_z(rz, rz2, rz3)) }
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inst_sve_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sme2_luti2_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI2_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} }
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emit_sme2_luti2_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti2_b_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sme2_luti4_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI4_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} }
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emit_sme2_luti4_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti4_b_z_z_z_i(rz, rz2, rz3, imm)) }
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inst_sme2_ld1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_ld1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_ld1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x2_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_st1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
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emit_sme2_st1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x4_z_p_m(rz, rz2, mem)) }
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inst_sme2_zip_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sme2_zip_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_zip_3_z_z_z(rz, rz2, rz3)) }
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inst_sme2_zip_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} }
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emit_sme2_zip_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_zip_4_z_z(rz, rz2)) }
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inst_sme2_uzp_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} }
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emit_sme2_uzp_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_uzp_3_z_z_z(rz, rz2, rz3)) }
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inst_sme2_uzp_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} }
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emit_sme2_uzp_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_uzp_4_z_z(rz, rz2)) }
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inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) }
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emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) }
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inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) }
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emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) }
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inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) }
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emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) }
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inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) }
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emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) }
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inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) }
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emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) }
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inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) }
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emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) }
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inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) }
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emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) }
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inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) }
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emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) }
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inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) }
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emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) }
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inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) }
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emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) }
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inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) }
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emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) }
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inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) }
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emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) }
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inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) }
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emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) }
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inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) }
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emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) }
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inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) }
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emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) }
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inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) }
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emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) }
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inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) }
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emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) }
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inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) }
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emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) }
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inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) }
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emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) }
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inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) }
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emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) }
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inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) }
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emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) }
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inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) }
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emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) }
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inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) }
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emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) }
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inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) }
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emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) }
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inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) }
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emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) }
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inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) }
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emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) }
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inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) }
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emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) }
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inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) }
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emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) }
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inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) }
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emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) }
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inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) }
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emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) }
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inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) }
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emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) }
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inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) }
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emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) }
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inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) }
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emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) }
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inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) }
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emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) }
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inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) }
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emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) }
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inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) }
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emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) }
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inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) }
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emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) }
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inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) }
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emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) }
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inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) }
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emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) }
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inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) }
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emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) }
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inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) }
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emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) }
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inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) }
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emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) }
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inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) }
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emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) }
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inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) }
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emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) }
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inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) }
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emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) }
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inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) }
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emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) }
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inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) }
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emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) }
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inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) }
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emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) }
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inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) }
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emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) }
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inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) }
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emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) }
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inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) }
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emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) }
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inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) }
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emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) }
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inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) }
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emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) }
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inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) }
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emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) }
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inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) }
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emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) }
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inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) }
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emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) }
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inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) }
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emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) }
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inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) }
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emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) }
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inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) }
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emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) }
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inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) }
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emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) }
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inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) }
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emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) }
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inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) }
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emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) }
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inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) }
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emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) }
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inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) }
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emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) }
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|
inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) }
|
|
emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) }
|
|
inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) }
|
|
emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) }
|
|
inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) }
|
|
emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) }
|
|
inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) }
|
|
emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) }
|
|
inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) }
|
|
emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) }
|
|
inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) }
|
|
emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) }
|
|
inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) }
|
|
emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) }
|
|
inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) }
|
|
emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) }
|
|
inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) }
|
|
emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) }
|
|
inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) }
|
|
emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) }
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|
inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) }
|
|
emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) }
|
|
inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) }
|
|
emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) }
|
|
inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) }
|
|
emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) }
|
|
inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) }
|
|
emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) }
|
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inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) }
|
|
emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) }
|
|
inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) }
|
|
emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) }
|
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inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) }
|
|
emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) }
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inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} }
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|
emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) }
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inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} }
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emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) }
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inst_prfm_lit_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM_LIT, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} }
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emit_prfm_lit_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_lit_i_l(imm, label)) }
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inst_mov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV_REG, dst, src) }
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emit_mov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_reg_r_r(dst, src)) }
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inst_mov_bitmask_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV_BITMASK, dst, imm) }
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emit_mov_bitmask_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_bitmask_r_i(dst, imm)) }
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inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) }
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emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) }
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inst_neg_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} }
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emit_neg_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_sr_r_sh(dst, src, src_shift, src_amount)) }
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inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} }
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emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) }
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inst_cmp_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} }
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emit_cmp_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_sr_r_sh(dst, src, src_shift, src_amount)) }
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inst_cmp_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} }
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emit_cmp_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_er_r_ex(dst, src, src_ext, src_amount)) }
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inst_cmp_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP_IMM, dst, imm) }
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emit_cmp_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_imm_r_i(dst, imm)) }
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inst_cmn_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} }
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emit_cmn_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_sr_r_sh(dst, src, src_shift, src_amount)) }
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inst_cmn_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} }
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emit_cmn_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_er_r_ex(dst, src, src_ext, src_amount)) }
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inst_cmn_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN_IMM, dst, imm) }
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emit_cmn_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_imm_r_i(dst, imm)) }
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inst_tst_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} }
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emit_tst_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_sr_r_sh(dst, src, src_shift, src_amount)) }
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// =============================================================================
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// Overload Groups
|
|
// =============================================================================
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|
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inst_add_imm :: inst_add_imm_r_r_i
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|
emit_add_imm :: emit_add_imm_r_r_i
|
|
inst_adds_imm :: inst_adds_imm_r_r_i
|
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emit_adds_imm :: emit_adds_imm_r_r_i
|
|
inst_sub_imm :: inst_sub_imm_r_r_i
|
|
emit_sub_imm :: emit_sub_imm_r_r_i
|
|
inst_subs_imm :: inst_subs_imm_r_r_i
|
|
emit_subs_imm :: emit_subs_imm_r_r_i
|
|
inst_movz :: inst_movz_r_i_i
|
|
emit_movz :: emit_movz_r_i_i
|
|
inst_movn :: inst_movn_r_i_i
|
|
emit_movn :: emit_movn_r_i_i
|
|
inst_movk :: inst_movk_r_i_i
|
|
emit_movk :: emit_movk_r_i_i
|
|
inst_adr :: inst_adr_r_l
|
|
emit_adr :: emit_adr_r_l
|
|
inst_adrp :: inst_adrp_r_l
|
|
emit_adrp :: emit_adrp_r_l
|
|
inst_add_sr :: inst_add_sr_r_r_sh
|
|
emit_add_sr :: emit_add_sr_r_r_sh
|
|
inst_adds_sr :: inst_adds_sr_r_r_sh
|
|
emit_adds_sr :: emit_adds_sr_r_r_sh
|
|
inst_sub_sr :: inst_sub_sr_r_r_sh
|
|
emit_sub_sr :: emit_sub_sr_r_r_sh
|
|
inst_subs_sr :: inst_subs_sr_r_r_sh
|
|
emit_subs_sr :: emit_subs_sr_r_r_sh
|
|
inst_and_sr :: inst_and_sr_r_r_sh
|
|
emit_and_sr :: emit_and_sr_r_r_sh
|
|
inst_ands_sr :: inst_ands_sr_r_r_sh
|
|
emit_ands_sr :: emit_ands_sr_r_r_sh
|
|
inst_orr_sr :: inst_orr_sr_r_r_sh
|
|
emit_orr_sr :: emit_orr_sr_r_r_sh
|
|
inst_eor_sr :: inst_eor_sr_r_r_sh
|
|
emit_eor_sr :: emit_eor_sr_r_r_sh
|
|
inst_bic_sr :: inst_bic_sr_r_r_sh
|
|
emit_bic_sr :: emit_bic_sr_r_r_sh
|
|
inst_bics_sr :: inst_bics_sr_r_r_sh
|
|
emit_bics_sr :: emit_bics_sr_r_r_sh
|
|
inst_orn_sr :: inst_orn_sr_r_r_sh
|
|
emit_orn_sr :: emit_orn_sr_r_r_sh
|
|
inst_eon_sr :: inst_eon_sr_r_r_sh
|
|
emit_eon_sr :: emit_eon_sr_r_r_sh
|
|
inst_add_er :: inst_add_er_r_r_ex
|
|
emit_add_er :: emit_add_er_r_r_ex
|
|
inst_adds_er :: inst_adds_er_r_r_ex
|
|
emit_adds_er :: emit_adds_er_r_r_ex
|
|
inst_sub_er :: inst_sub_er_r_r_ex
|
|
emit_sub_er :: emit_sub_er_r_r_ex
|
|
inst_subs_er :: inst_subs_er_r_r_ex
|
|
emit_subs_er :: emit_subs_er_r_r_ex
|
|
inst_lslv :: inst_lslv_r_r_r
|
|
emit_lslv :: emit_lslv_r_r_r
|
|
inst_lsrv :: inst_lsrv_r_r_r
|
|
emit_lsrv :: emit_lsrv_r_r_r
|
|
inst_asrv :: inst_asrv_r_r_r
|
|
emit_asrv :: emit_asrv_r_r_r
|
|
inst_rorv :: inst_rorv_r_r_r
|
|
emit_rorv :: emit_rorv_r_r_r
|
|
inst_udiv :: inst_udiv_r_r_r
|
|
emit_udiv :: emit_udiv_r_r_r
|
|
inst_sdiv :: inst_sdiv_r_r_r
|
|
emit_sdiv :: emit_sdiv_r_r_r
|
|
inst_madd :: inst_madd_r_r_r_r
|
|
emit_madd :: emit_madd_r_r_r_r
|
|
inst_msub :: inst_msub_r_r_r_r
|
|
emit_msub :: emit_msub_r_r_r_r
|
|
inst_smaddl :: inst_smaddl_r_r_r_r
|
|
emit_smaddl :: emit_smaddl_r_r_r_r
|
|
inst_smsubl :: inst_smsubl_r_r_r_r
|
|
emit_smsubl :: emit_smsubl_r_r_r_r
|
|
inst_umaddl :: inst_umaddl_r_r_r_r
|
|
emit_umaddl :: emit_umaddl_r_r_r_r
|
|
inst_umsubl :: inst_umsubl_r_r_r_r
|
|
emit_umsubl :: emit_umsubl_r_r_r_r
|
|
inst_smulh :: inst_smulh_r_r_r
|
|
emit_smulh :: emit_smulh_r_r_r
|
|
inst_umulh :: inst_umulh_r_r_r
|
|
emit_umulh :: emit_umulh_r_r_r
|
|
inst_clz :: inst_clz_r_r
|
|
emit_clz :: emit_clz_r_r
|
|
inst_cls :: inst_cls_r_r
|
|
emit_cls :: emit_cls_r_r
|
|
inst_rbit :: inst_rbit_r_r
|
|
emit_rbit :: emit_rbit_r_r
|
|
inst_rev :: inst_rev_r_r
|
|
emit_rev :: emit_rev_r_r
|
|
inst_rev16 :: inst_rev16_r_r
|
|
emit_rev16 :: emit_rev16_r_r
|
|
inst_rev32 :: inst_rev32_r_r
|
|
emit_rev32 :: emit_rev32_r_r
|
|
inst_csel :: inst_csel_r_r_r_c
|
|
emit_csel :: emit_csel_r_r_r_c
|
|
inst_csinc :: inst_csinc_r_r_r_c
|
|
emit_csinc :: emit_csinc_r_r_r_c
|
|
inst_csinv :: inst_csinv_r_r_r_c
|
|
emit_csinv :: emit_csinv_r_r_r_c
|
|
inst_csneg :: inst_csneg_r_r_r_c
|
|
emit_csneg :: emit_csneg_r_r_r_c
|
|
inst_ccmp_reg :: inst_ccmp_reg_r_r_i_c
|
|
emit_ccmp_reg :: emit_ccmp_reg_r_r_i_c
|
|
inst_ccmp_imm :: inst_ccmp_imm_r_i_i_c
|
|
emit_ccmp_imm :: emit_ccmp_imm_r_i_i_c
|
|
inst_ccmn_reg :: inst_ccmn_reg_r_r_i_c
|
|
emit_ccmn_reg :: emit_ccmn_reg_r_r_i_c
|
|
inst_ccmn_imm :: inst_ccmn_imm_r_i_i_c
|
|
emit_ccmn_imm :: emit_ccmn_imm_r_i_i_c
|
|
inst_extr :: inst_extr_r_r_r_i
|
|
emit_extr :: emit_extr_r_r_r_i
|
|
inst_b :: inst_b_l
|
|
emit_b :: emit_b_l
|
|
inst_bl :: inst_bl_l
|
|
emit_bl :: emit_bl_l
|
|
inst_br :: inst_br_r
|
|
emit_br :: emit_br_r
|
|
inst_blr :: inst_blr_r
|
|
emit_blr :: emit_blr_r
|
|
inst_ret :: proc{ inst_ret_r, inst_ret_none }
|
|
emit_ret :: proc{ emit_ret_r, emit_ret_none }
|
|
inst_b_cond :: inst_b_cond_c_l
|
|
emit_b_cond :: emit_b_cond_c_l
|
|
inst_cbz :: inst_cbz_r_l
|
|
emit_cbz :: emit_cbz_r_l
|
|
inst_cbnz :: inst_cbnz_r_l
|
|
emit_cbnz :: emit_cbnz_r_l
|
|
inst_tbz :: inst_tbz_r_i_l
|
|
emit_tbz :: emit_tbz_r_i_l
|
|
inst_tbnz :: inst_tbnz_r_i_l
|
|
emit_tbnz :: emit_tbnz_r_i_l
|
|
inst_ldr :: inst_ldr_r_m
|
|
emit_ldr :: emit_ldr_r_m
|
|
inst_str :: inst_str_r_m
|
|
emit_str :: emit_str_r_m
|
|
inst_ldrb :: inst_ldrb_r_m
|
|
emit_ldrb :: emit_ldrb_r_m
|
|
inst_strb :: inst_strb_r_m
|
|
emit_strb :: emit_strb_r_m
|
|
inst_ldrsb :: inst_ldrsb_r_m
|
|
emit_ldrsb :: emit_ldrsb_r_m
|
|
inst_ldrh :: inst_ldrh_r_m
|
|
emit_ldrh :: emit_ldrh_r_m
|
|
inst_strh :: inst_strh_r_m
|
|
emit_strh :: emit_strh_r_m
|
|
inst_ldrsh :: inst_ldrsh_r_m
|
|
emit_ldrsh :: emit_ldrsh_r_m
|
|
inst_ldrsw :: inst_ldrsw_r_m
|
|
emit_ldrsw :: emit_ldrsw_r_m
|
|
inst_ldp :: inst_ldp_r_r_m
|
|
emit_ldp :: emit_ldp_r_r_m
|
|
inst_stp :: inst_stp_r_r_m
|
|
emit_stp :: emit_stp_r_r_m
|
|
inst_ldpsw :: inst_ldpsw_r_r_m
|
|
emit_ldpsw :: emit_ldpsw_r_r_m
|
|
inst_ldr_lit :: inst_ldr_lit_r_l
|
|
emit_ldr_lit :: emit_ldr_lit_r_l
|
|
inst_ldar :: inst_ldar_r_m
|
|
emit_ldar :: emit_ldar_r_m
|
|
inst_stlr :: inst_stlr_r_m
|
|
emit_stlr :: emit_stlr_r_m
|
|
inst_ldarb :: inst_ldarb_r_m
|
|
emit_ldarb :: emit_ldarb_r_m
|
|
inst_stlrb :: inst_stlrb_r_m
|
|
emit_stlrb :: emit_stlrb_r_m
|
|
inst_ldarh :: inst_ldarh_r_m
|
|
emit_ldarh :: emit_ldarh_r_m
|
|
inst_stlrh :: inst_stlrh_r_m
|
|
emit_stlrh :: emit_stlrh_r_m
|
|
inst_ldxr :: inst_ldxr_r_m
|
|
emit_ldxr :: emit_ldxr_r_m
|
|
inst_stxr :: inst_stxr_r_r_m
|
|
emit_stxr :: emit_stxr_r_r_m
|
|
inst_ldaxr :: inst_ldaxr_r_m
|
|
emit_ldaxr :: emit_ldaxr_r_m
|
|
inst_stlxr :: inst_stlxr_r_r_m
|
|
emit_stlxr :: emit_stlxr_r_r_m
|
|
inst_nop :: inst_nop_none
|
|
emit_nop :: emit_nop_none
|
|
inst_yield :: inst_yield_none
|
|
emit_yield :: emit_yield_none
|
|
inst_wfe :: inst_wfe_none
|
|
emit_wfe :: emit_wfe_none
|
|
inst_wfi :: inst_wfi_none
|
|
emit_wfi :: emit_wfi_none
|
|
inst_sev :: inst_sev_none
|
|
emit_sev :: emit_sev_none
|
|
inst_sevl :: inst_sevl_none
|
|
emit_sevl :: emit_sevl_none
|
|
inst_hint :: inst_hint_i
|
|
emit_hint :: emit_hint_i
|
|
inst_mrs :: inst_mrs_r_i
|
|
emit_mrs :: emit_mrs_r_i
|
|
inst_msr_imm :: inst_msr_imm_i_i
|
|
emit_msr_imm :: emit_msr_imm_i_i
|
|
inst_msr_reg :: inst_msr_reg_i_r
|
|
emit_msr_reg :: emit_msr_reg_i_r
|
|
inst_isb :: inst_isb_i
|
|
emit_isb :: emit_isb_i
|
|
inst_dsb :: inst_dsb_i
|
|
emit_dsb :: emit_dsb_i
|
|
inst_dmb :: inst_dmb_i
|
|
emit_dmb :: emit_dmb_i
|
|
inst_svc :: inst_svc_i
|
|
emit_svc :: emit_svc_i
|
|
inst_hvc :: inst_hvc_i
|
|
emit_hvc :: emit_hvc_i
|
|
inst_smc :: inst_smc_i
|
|
emit_smc :: emit_smc_i
|
|
inst_brk :: inst_brk_i
|
|
emit_brk :: emit_brk_i
|
|
inst_hlt :: inst_hlt_i
|
|
emit_hlt :: emit_hlt_i
|
|
inst_eret :: inst_eret_none
|
|
emit_eret :: emit_eret_none
|
|
inst_fmov_reg :: inst_fmov_reg_r_r
|
|
emit_fmov_reg :: emit_fmov_reg_r_r
|
|
inst_fmov_imm :: inst_fmov_imm_r_i
|
|
emit_fmov_imm :: emit_fmov_imm_r_i
|
|
inst_fmov_gen :: inst_fmov_gen_r_r
|
|
emit_fmov_gen :: emit_fmov_gen_r_r
|
|
inst_fabs :: inst_fabs_r_r
|
|
emit_fabs :: emit_fabs_r_r
|
|
inst_fneg :: inst_fneg_r_r
|
|
emit_fneg :: emit_fneg_r_r
|
|
inst_fsqrt :: inst_fsqrt_r_r
|
|
emit_fsqrt :: emit_fsqrt_r_r
|
|
inst_fadd :: inst_fadd_r_r_r
|
|
emit_fadd :: emit_fadd_r_r_r
|
|
inst_fsub :: inst_fsub_r_r_r
|
|
emit_fsub :: emit_fsub_r_r_r
|
|
inst_fmul :: inst_fmul_r_r_r
|
|
emit_fmul :: emit_fmul_r_r_r
|
|
inst_fdiv :: inst_fdiv_r_r_r
|
|
emit_fdiv :: emit_fdiv_r_r_r
|
|
inst_fnmul :: inst_fnmul_r_r_r
|
|
emit_fnmul :: emit_fnmul_r_r_r
|
|
inst_fmadd :: inst_fmadd_r_r_r_r
|
|
emit_fmadd :: emit_fmadd_r_r_r_r
|
|
inst_fmsub :: inst_fmsub_r_r_r_r
|
|
emit_fmsub :: emit_fmsub_r_r_r_r
|
|
inst_fnmadd :: inst_fnmadd_r_r_r_r
|
|
emit_fnmadd :: emit_fnmadd_r_r_r_r
|
|
inst_fnmsub :: inst_fnmsub_r_r_r_r
|
|
emit_fnmsub :: emit_fnmsub_r_r_r_r
|
|
inst_fcmp :: inst_fcmp_r_r
|
|
emit_fcmp :: emit_fcmp_r_r
|
|
inst_fcmpe :: inst_fcmpe_r_r
|
|
emit_fcmpe :: emit_fcmpe_r_r
|
|
inst_fcsel :: inst_fcsel_r_r_r_c
|
|
emit_fcsel :: emit_fcsel_r_r_r_c
|
|
inst_fmax :: inst_fmax_r_r_r
|
|
emit_fmax :: emit_fmax_r_r_r
|
|
inst_fmin :: inst_fmin_r_r_r
|
|
emit_fmin :: emit_fmin_r_r_r
|
|
inst_fmaxnm :: inst_fmaxnm_r_r_r
|
|
emit_fmaxnm :: emit_fmaxnm_r_r_r
|
|
inst_fminnm :: inst_fminnm_r_r_r
|
|
emit_fminnm :: emit_fminnm_r_r_r
|
|
inst_fcvt :: inst_fcvt_r_r
|
|
emit_fcvt :: emit_fcvt_r_r
|
|
inst_scvtf :: inst_scvtf_r_r
|
|
emit_scvtf :: emit_scvtf_r_r
|
|
inst_ucvtf :: inst_ucvtf_r_r
|
|
emit_ucvtf :: emit_ucvtf_r_r
|
|
inst_fcvtzs :: inst_fcvtzs_r_r
|
|
emit_fcvtzs :: emit_fcvtzs_r_r
|
|
inst_fcvtzu :: inst_fcvtzu_r_r
|
|
emit_fcvtzu :: emit_fcvtzu_r_r
|
|
inst_fcvtas :: inst_fcvtas_r_r
|
|
emit_fcvtas :: emit_fcvtas_r_r
|
|
inst_fcvtau :: inst_fcvtau_r_r
|
|
emit_fcvtau :: emit_fcvtau_r_r
|
|
inst_fcvtns :: inst_fcvtns_r_r
|
|
emit_fcvtns :: emit_fcvtns_r_r
|
|
inst_fcvtnu :: inst_fcvtnu_r_r
|
|
emit_fcvtnu :: emit_fcvtnu_r_r
|
|
inst_fcvtps :: inst_fcvtps_r_r
|
|
emit_fcvtps :: emit_fcvtps_r_r
|
|
inst_fcvtpu :: inst_fcvtpu_r_r
|
|
emit_fcvtpu :: emit_fcvtpu_r_r
|
|
inst_fcvtms :: inst_fcvtms_r_r
|
|
emit_fcvtms :: emit_fcvtms_r_r
|
|
inst_fcvtmu :: inst_fcvtmu_r_r
|
|
emit_fcvtmu :: emit_fcvtmu_r_r
|
|
inst_frinta :: inst_frinta_r_r
|
|
emit_frinta :: emit_frinta_r_r
|
|
inst_frinti :: inst_frinti_r_r
|
|
emit_frinti :: emit_frinti_r_r
|
|
inst_frintm :: inst_frintm_r_r
|
|
emit_frintm :: emit_frintm_r_r
|
|
inst_frintn :: inst_frintn_r_r
|
|
emit_frintn :: emit_frintn_r_r
|
|
inst_frintp :: inst_frintp_r_r
|
|
emit_frintp :: emit_frintp_r_r
|
|
inst_frintx :: inst_frintx_r_r
|
|
emit_frintx :: emit_frintx_r_r
|
|
inst_frintz :: inst_frintz_r_r
|
|
emit_frintz :: emit_frintz_r_r
|
|
inst_and_imm :: inst_and_imm_r_r_i
|
|
emit_and_imm :: emit_and_imm_r_r_i
|
|
inst_ands_imm :: inst_ands_imm_r_r_i
|
|
emit_ands_imm :: emit_ands_imm_r_r_i
|
|
inst_orr_imm :: inst_orr_imm_r_r_i
|
|
emit_orr_imm :: emit_orr_imm_r_r_i
|
|
inst_eor_imm :: inst_eor_imm_r_r_i
|
|
emit_eor_imm :: emit_eor_imm_r_r_i
|
|
inst_tst_imm :: inst_tst_imm_r_i
|
|
emit_tst_imm :: emit_tst_imm_r_i
|
|
inst_ldur :: inst_ldur_r_m
|
|
emit_ldur :: emit_ldur_r_m
|
|
inst_stur :: inst_stur_r_m
|
|
emit_stur :: emit_stur_r_m
|
|
inst_ldurb :: inst_ldurb_r_m
|
|
emit_ldurb :: emit_ldurb_r_m
|
|
inst_sturb :: inst_sturb_r_m
|
|
emit_sturb :: emit_sturb_r_m
|
|
inst_ldursb :: inst_ldursb_r_m
|
|
emit_ldursb :: emit_ldursb_r_m
|
|
inst_ldurh :: inst_ldurh_r_m
|
|
emit_ldurh :: emit_ldurh_r_m
|
|
inst_sturh :: inst_sturh_r_m
|
|
emit_sturh :: emit_sturh_r_m
|
|
inst_ldursh :: inst_ldursh_r_m
|
|
emit_ldursh :: emit_ldursh_r_m
|
|
inst_ldursw :: inst_ldursw_r_m
|
|
emit_ldursw :: emit_ldursw_r_m
|
|
inst_ldr_pre :: inst_ldr_pre_r_m
|
|
emit_ldr_pre :: emit_ldr_pre_r_m
|
|
inst_str_pre :: inst_str_pre_r_m
|
|
emit_str_pre :: emit_str_pre_r_m
|
|
inst_ldr_post :: inst_ldr_post_r_m
|
|
emit_ldr_post :: emit_ldr_post_r_m
|
|
inst_str_post :: inst_str_post_r_m
|
|
emit_str_post :: emit_str_post_r_m
|
|
inst_ldrb_pre :: inst_ldrb_pre_r_m
|
|
emit_ldrb_pre :: emit_ldrb_pre_r_m
|
|
inst_strb_pre :: inst_strb_pre_r_m
|
|
emit_strb_pre :: emit_strb_pre_r_m
|
|
inst_ldrb_post :: inst_ldrb_post_r_m
|
|
emit_ldrb_post :: emit_ldrb_post_r_m
|
|
inst_strb_post :: inst_strb_post_r_m
|
|
emit_strb_post :: emit_strb_post_r_m
|
|
inst_ldrh_pre :: inst_ldrh_pre_r_m
|
|
emit_ldrh_pre :: emit_ldrh_pre_r_m
|
|
inst_strh_pre :: inst_strh_pre_r_m
|
|
emit_strh_pre :: emit_strh_pre_r_m
|
|
inst_ldrh_post :: inst_ldrh_post_r_m
|
|
emit_ldrh_post :: emit_ldrh_post_r_m
|
|
inst_strh_post :: inst_strh_post_r_m
|
|
emit_strh_post :: emit_strh_post_r_m
|
|
inst_ldr_reg :: inst_ldr_reg_r_m
|
|
emit_ldr_reg :: emit_ldr_reg_r_m
|
|
inst_str_reg :: inst_str_reg_r_m
|
|
emit_str_reg :: emit_str_reg_r_m
|
|
inst_ldrb_reg :: inst_ldrb_reg_r_m
|
|
emit_ldrb_reg :: emit_ldrb_reg_r_m
|
|
inst_strb_reg :: inst_strb_reg_r_m
|
|
emit_strb_reg :: emit_strb_reg_r_m
|
|
inst_ldrh_reg :: inst_ldrh_reg_r_m
|
|
emit_ldrh_reg :: emit_ldrh_reg_r_m
|
|
inst_strh_reg :: inst_strh_reg_r_m
|
|
emit_strh_reg :: emit_strh_reg_r_m
|
|
inst_ldrsb_reg :: inst_ldrsb_reg_r_m
|
|
emit_ldrsb_reg :: emit_ldrsb_reg_r_m
|
|
inst_ldrsh_reg :: inst_ldrsh_reg_r_m
|
|
emit_ldrsh_reg :: emit_ldrsh_reg_r_m
|
|
inst_ldrsw_reg :: inst_ldrsw_reg_r_m
|
|
emit_ldrsw_reg :: emit_ldrsw_reg_r_m
|
|
inst_ldp_pre :: inst_ldp_pre_r_r_m
|
|
emit_ldp_pre :: emit_ldp_pre_r_r_m
|
|
inst_stp_pre :: inst_stp_pre_r_r_m
|
|
emit_stp_pre :: emit_stp_pre_r_r_m
|
|
inst_ldp_post :: inst_ldp_post_r_r_m
|
|
emit_ldp_post :: emit_ldp_post_r_r_m
|
|
inst_stp_post :: inst_stp_post_r_r_m
|
|
emit_stp_post :: emit_stp_post_r_r_m
|
|
inst_ldpsw_pre :: inst_ldpsw_pre_r_r_m
|
|
emit_ldpsw_pre :: emit_ldpsw_pre_r_r_m
|
|
inst_ldpsw_post :: inst_ldpsw_post_r_r_m
|
|
emit_ldpsw_post :: emit_ldpsw_post_r_r_m
|
|
inst_ldnp :: inst_ldnp_r_r_m
|
|
emit_ldnp :: emit_ldnp_r_r_m
|
|
inst_stnp :: inst_stnp_r_r_m
|
|
emit_stnp :: emit_stnp_r_r_m
|
|
inst_ldxp :: inst_ldxp_r_r_m
|
|
emit_ldxp :: emit_ldxp_r_r_m
|
|
inst_stxp :: inst_stxp_r_r_r_m
|
|
emit_stxp :: emit_stxp_r_r_r_m
|
|
inst_ldaxp :: inst_ldaxp_r_r_m
|
|
emit_ldaxp :: emit_ldaxp_r_r_m
|
|
inst_stlxp :: inst_stlxp_r_r_r_m
|
|
emit_stlxp :: emit_stlxp_r_r_r_m
|
|
inst_ldxrb :: inst_ldxrb_r_m
|
|
emit_ldxrb :: emit_ldxrb_r_m
|
|
inst_stxrb :: inst_stxrb_r_r_m
|
|
emit_stxrb :: emit_stxrb_r_r_m
|
|
inst_ldaxrb :: inst_ldaxrb_r_m
|
|
emit_ldaxrb :: emit_ldaxrb_r_m
|
|
inst_stlxrb :: inst_stlxrb_r_r_m
|
|
emit_stlxrb :: emit_stlxrb_r_r_m
|
|
inst_ldxrh :: inst_ldxrh_r_m
|
|
emit_ldxrh :: emit_ldxrh_r_m
|
|
inst_stxrh :: inst_stxrh_r_r_m
|
|
emit_stxrh :: emit_stxrh_r_r_m
|
|
inst_ldaxrh :: inst_ldaxrh_r_m
|
|
emit_ldaxrh :: emit_ldaxrh_r_m
|
|
inst_stlxrh :: inst_stlxrh_r_r_m
|
|
emit_stlxrh :: emit_stlxrh_r_r_m
|
|
inst_ldapr :: inst_ldapr_r_m
|
|
emit_ldapr :: emit_ldapr_r_m
|
|
inst_ldaprb :: inst_ldaprb_r_m
|
|
emit_ldaprb :: emit_ldaprb_r_m
|
|
inst_ldaprh :: inst_ldaprh_r_m
|
|
emit_ldaprh :: emit_ldaprh_r_m
|
|
inst_ldadd :: inst_ldadd_r_r_m
|
|
emit_ldadd :: emit_ldadd_r_r_m
|
|
inst_ldadda :: inst_ldadda_r_r_m
|
|
emit_ldadda :: emit_ldadda_r_r_m
|
|
inst_ldaddl :: inst_ldaddl_r_r_m
|
|
emit_ldaddl :: emit_ldaddl_r_r_m
|
|
inst_ldaddal :: inst_ldaddal_r_r_m
|
|
emit_ldaddal :: emit_ldaddal_r_r_m
|
|
inst_ldclr :: inst_ldclr_r_r_m
|
|
emit_ldclr :: emit_ldclr_r_r_m
|
|
inst_ldclra :: inst_ldclra_r_r_m
|
|
emit_ldclra :: emit_ldclra_r_r_m
|
|
inst_ldclrl :: inst_ldclrl_r_r_m
|
|
emit_ldclrl :: emit_ldclrl_r_r_m
|
|
inst_ldclral :: inst_ldclral_r_r_m
|
|
emit_ldclral :: emit_ldclral_r_r_m
|
|
inst_ldeor :: inst_ldeor_r_r_m
|
|
emit_ldeor :: emit_ldeor_r_r_m
|
|
inst_ldeora :: inst_ldeora_r_r_m
|
|
emit_ldeora :: emit_ldeora_r_r_m
|
|
inst_ldeorl :: inst_ldeorl_r_r_m
|
|
emit_ldeorl :: emit_ldeorl_r_r_m
|
|
inst_ldeoral :: inst_ldeoral_r_r_m
|
|
emit_ldeoral :: emit_ldeoral_r_r_m
|
|
inst_ldset :: inst_ldset_r_r_m
|
|
emit_ldset :: emit_ldset_r_r_m
|
|
inst_ldseta :: inst_ldseta_r_r_m
|
|
emit_ldseta :: emit_ldseta_r_r_m
|
|
inst_ldsetl :: inst_ldsetl_r_r_m
|
|
emit_ldsetl :: emit_ldsetl_r_r_m
|
|
inst_ldsetal :: inst_ldsetal_r_r_m
|
|
emit_ldsetal :: emit_ldsetal_r_r_m
|
|
inst_ldsmax :: inst_ldsmax_r_r_m
|
|
emit_ldsmax :: emit_ldsmax_r_r_m
|
|
inst_ldsmaxa :: inst_ldsmaxa_r_r_m
|
|
emit_ldsmaxa :: emit_ldsmaxa_r_r_m
|
|
inst_ldsmaxl :: inst_ldsmaxl_r_r_m
|
|
emit_ldsmaxl :: emit_ldsmaxl_r_r_m
|
|
inst_ldsmaxal :: inst_ldsmaxal_r_r_m
|
|
emit_ldsmaxal :: emit_ldsmaxal_r_r_m
|
|
inst_ldsmin :: inst_ldsmin_r_r_m
|
|
emit_ldsmin :: emit_ldsmin_r_r_m
|
|
inst_ldsmina :: inst_ldsmina_r_r_m
|
|
emit_ldsmina :: emit_ldsmina_r_r_m
|
|
inst_ldsminl :: inst_ldsminl_r_r_m
|
|
emit_ldsminl :: emit_ldsminl_r_r_m
|
|
inst_ldsminal :: inst_ldsminal_r_r_m
|
|
emit_ldsminal :: emit_ldsminal_r_r_m
|
|
inst_ldumax :: inst_ldumax_r_r_m
|
|
emit_ldumax :: emit_ldumax_r_r_m
|
|
inst_ldumaxa :: inst_ldumaxa_r_r_m
|
|
emit_ldumaxa :: emit_ldumaxa_r_r_m
|
|
inst_ldumaxl :: inst_ldumaxl_r_r_m
|
|
emit_ldumaxl :: emit_ldumaxl_r_r_m
|
|
inst_ldumaxal :: inst_ldumaxal_r_r_m
|
|
emit_ldumaxal :: emit_ldumaxal_r_r_m
|
|
inst_ldumin :: inst_ldumin_r_r_m
|
|
emit_ldumin :: emit_ldumin_r_r_m
|
|
inst_ldumina :: inst_ldumina_r_r_m
|
|
emit_ldumina :: emit_ldumina_r_r_m
|
|
inst_lduminl :: inst_lduminl_r_r_m
|
|
emit_lduminl :: emit_lduminl_r_r_m
|
|
inst_lduminal :: inst_lduminal_r_r_m
|
|
emit_lduminal :: emit_lduminal_r_r_m
|
|
inst_swp :: inst_swp_r_r_m
|
|
emit_swp :: emit_swp_r_r_m
|
|
inst_swpa :: inst_swpa_r_r_m
|
|
emit_swpa :: emit_swpa_r_r_m
|
|
inst_swpl :: inst_swpl_r_r_m
|
|
emit_swpl :: emit_swpl_r_r_m
|
|
inst_swpal :: inst_swpal_r_r_m
|
|
emit_swpal :: emit_swpal_r_r_m
|
|
inst_cas :: inst_cas_r_r_m
|
|
emit_cas :: emit_cas_r_r_m
|
|
inst_casa :: inst_casa_r_r_m
|
|
emit_casa :: emit_casa_r_r_m
|
|
inst_casl :: inst_casl_r_r_m
|
|
emit_casl :: emit_casl_r_r_m
|
|
inst_casal :: inst_casal_r_r_m
|
|
emit_casal :: emit_casal_r_r_m
|
|
inst_casb :: inst_casb_r_r_m
|
|
emit_casb :: emit_casb_r_r_m
|
|
inst_casab :: inst_casab_r_r_m
|
|
emit_casab :: emit_casab_r_r_m
|
|
inst_caslb :: inst_caslb_r_r_m
|
|
emit_caslb :: emit_caslb_r_r_m
|
|
inst_casalb :: inst_casalb_r_r_m
|
|
emit_casalb :: emit_casalb_r_r_m
|
|
inst_cash :: inst_cash_r_r_m
|
|
emit_cash :: emit_cash_r_r_m
|
|
inst_casah :: inst_casah_r_r_m
|
|
emit_casah :: emit_casah_r_r_m
|
|
inst_caslh :: inst_caslh_r_r_m
|
|
emit_caslh :: emit_caslh_r_r_m
|
|
inst_casalh :: inst_casalh_r_r_m
|
|
emit_casalh :: emit_casalh_r_r_m
|
|
inst_casp :: inst_casp_r_r_m
|
|
emit_casp :: emit_casp_r_r_m
|
|
inst_caspa :: inst_caspa_r_r_m
|
|
emit_caspa :: emit_caspa_r_r_m
|
|
inst_caspl :: inst_caspl_r_r_m
|
|
emit_caspl :: emit_caspl_r_r_m
|
|
inst_caspal :: inst_caspal_r_r_m
|
|
emit_caspal :: emit_caspal_r_r_m
|
|
inst_pacia :: inst_pacia_r_r
|
|
emit_pacia :: emit_pacia_r_r
|
|
inst_pacib :: inst_pacib_r_r
|
|
emit_pacib :: emit_pacib_r_r
|
|
inst_pacda :: inst_pacda_r_r
|
|
emit_pacda :: emit_pacda_r_r
|
|
inst_pacdb :: inst_pacdb_r_r
|
|
emit_pacdb :: emit_pacdb_r_r
|
|
inst_paciza :: inst_paciza_r
|
|
emit_paciza :: emit_paciza_r
|
|
inst_pacizb :: inst_pacizb_r
|
|
emit_pacizb :: emit_pacizb_r
|
|
inst_pacdza :: inst_pacdza_r
|
|
emit_pacdza :: emit_pacdza_r
|
|
inst_pacdzb :: inst_pacdzb_r
|
|
emit_pacdzb :: emit_pacdzb_r
|
|
inst_autia :: inst_autia_r_r
|
|
emit_autia :: emit_autia_r_r
|
|
inst_autib :: inst_autib_r_r
|
|
emit_autib :: emit_autib_r_r
|
|
inst_autda :: inst_autda_r_r
|
|
emit_autda :: emit_autda_r_r
|
|
inst_autdb :: inst_autdb_r_r
|
|
emit_autdb :: emit_autdb_r_r
|
|
inst_autiza :: inst_autiza_r
|
|
emit_autiza :: emit_autiza_r
|
|
inst_autizb :: inst_autizb_r
|
|
emit_autizb :: emit_autizb_r
|
|
inst_autdza :: inst_autdza_r
|
|
emit_autdza :: emit_autdza_r
|
|
inst_autdzb :: inst_autdzb_r
|
|
emit_autdzb :: emit_autdzb_r
|
|
inst_paciasp :: inst_paciasp_none
|
|
emit_paciasp :: emit_paciasp_none
|
|
inst_pacibsp :: inst_pacibsp_none
|
|
emit_pacibsp :: emit_pacibsp_none
|
|
inst_autiasp :: inst_autiasp_none
|
|
emit_autiasp :: emit_autiasp_none
|
|
inst_autibsp :: inst_autibsp_none
|
|
emit_autibsp :: emit_autibsp_none
|
|
inst_pacia1716 :: inst_pacia1716_none
|
|
emit_pacia1716 :: emit_pacia1716_none
|
|
inst_pacib1716 :: inst_pacib1716_none
|
|
emit_pacib1716 :: emit_pacib1716_none
|
|
inst_autia1716 :: inst_autia1716_none
|
|
emit_autia1716 :: emit_autia1716_none
|
|
inst_autib1716 :: inst_autib1716_none
|
|
emit_autib1716 :: emit_autib1716_none
|
|
inst_pacga :: inst_pacga_r_r_r
|
|
emit_pacga :: emit_pacga_r_r_r
|
|
inst_xpaci :: inst_xpaci_r
|
|
emit_xpaci :: emit_xpaci_r
|
|
inst_xpacd :: inst_xpacd_r
|
|
emit_xpacd :: emit_xpacd_r
|
|
inst_xpaclri :: inst_xpaclri_none
|
|
emit_xpaclri :: emit_xpaclri_none
|
|
inst_retaa :: inst_retaa_none
|
|
emit_retaa :: emit_retaa_none
|
|
inst_retab :: inst_retab_none
|
|
emit_retab :: emit_retab_none
|
|
inst_braa :: inst_braa_r_r
|
|
emit_braa :: emit_braa_r_r
|
|
inst_brab :: inst_brab_r_r
|
|
emit_brab :: emit_brab_r_r
|
|
inst_braaz :: inst_braaz_r
|
|
emit_braaz :: emit_braaz_r
|
|
inst_brabz :: inst_brabz_r
|
|
emit_brabz :: emit_brabz_r
|
|
inst_blraa :: inst_blraa_r_r
|
|
emit_blraa :: emit_blraa_r_r
|
|
inst_blrab :: inst_blrab_r_r
|
|
emit_blrab :: emit_blrab_r_r
|
|
inst_blraaz :: inst_blraaz_r
|
|
emit_blraaz :: emit_blraaz_r
|
|
inst_blrabz :: inst_blrabz_r
|
|
emit_blrabz :: emit_blrabz_r
|
|
inst_eretaa :: inst_eretaa_none
|
|
emit_eretaa :: emit_eretaa_none
|
|
inst_eretab :: inst_eretab_none
|
|
emit_eretab :: emit_eretab_none
|
|
inst_bti :: inst_bti_i
|
|
emit_bti :: emit_bti_i
|
|
inst_irg :: inst_irg_r_r_r
|
|
emit_irg :: emit_irg_r_r_r
|
|
inst_addg :: inst_addg_r_r_i_i
|
|
emit_addg :: emit_addg_r_r_i_i
|
|
inst_subg :: inst_subg_r_r_i_i
|
|
emit_subg :: emit_subg_r_r_i_i
|
|
inst_gmi :: inst_gmi_r_r_r
|
|
emit_gmi :: emit_gmi_r_r_r
|
|
inst_subp :: inst_subp_r_r_r
|
|
emit_subp :: emit_subp_r_r_r
|
|
inst_subps :: inst_subps_r_r_r
|
|
emit_subps :: emit_subps_r_r_r
|
|
inst_ldg :: inst_ldg_r_m
|
|
emit_ldg :: emit_ldg_r_m
|
|
inst_stg :: inst_stg_r_m
|
|
emit_stg :: emit_stg_r_m
|
|
inst_st2g :: inst_st2g_r_m
|
|
emit_st2g :: emit_st2g_r_m
|
|
inst_stzg :: inst_stzg_r_m
|
|
emit_stzg :: emit_stzg_r_m
|
|
inst_stz2g :: inst_stz2g_r_m
|
|
emit_stz2g :: emit_stz2g_r_m
|
|
inst_stgp :: inst_stgp_r_r_m
|
|
emit_stgp :: emit_stgp_r_r_m
|
|
inst_ldgm :: inst_ldgm_r_m
|
|
emit_ldgm :: emit_ldgm_r_m
|
|
inst_stgm :: inst_stgm_r_m
|
|
emit_stgm :: emit_stgm_r_m
|
|
inst_stzgm :: inst_stzgm_r_m
|
|
emit_stzgm :: emit_stzgm_r_m
|
|
inst_crc32b :: inst_crc32b_r_r_r
|
|
emit_crc32b :: emit_crc32b_r_r_r
|
|
inst_crc32h :: inst_crc32h_r_r_r
|
|
emit_crc32h :: emit_crc32h_r_r_r
|
|
inst_crc32w :: inst_crc32w_r_r_r
|
|
emit_crc32w :: emit_crc32w_r_r_r
|
|
inst_crc32x :: inst_crc32x_r_r_r
|
|
emit_crc32x :: emit_crc32x_r_r_r
|
|
inst_crc32cb :: inst_crc32cb_r_r_r
|
|
emit_crc32cb :: emit_crc32cb_r_r_r
|
|
inst_crc32ch :: inst_crc32ch_r_r_r
|
|
emit_crc32ch :: emit_crc32ch_r_r_r
|
|
inst_crc32cw :: inst_crc32cw_r_r_r
|
|
emit_crc32cw :: emit_crc32cw_r_r_r
|
|
inst_crc32cx :: inst_crc32cx_r_r_r
|
|
emit_crc32cx :: emit_crc32cx_r_r_r
|
|
inst_aese :: inst_aese_r_r
|
|
emit_aese :: emit_aese_r_r
|
|
inst_aesd :: inst_aesd_r_r
|
|
emit_aesd :: emit_aesd_r_r
|
|
inst_aesmc :: inst_aesmc_r_r
|
|
emit_aesmc :: emit_aesmc_r_r
|
|
inst_aesimc :: inst_aesimc_r_r
|
|
emit_aesimc :: emit_aesimc_r_r
|
|
inst_sha1h :: inst_sha1h_r_r
|
|
emit_sha1h :: emit_sha1h_r_r
|
|
inst_sha1c :: inst_sha1c_r_r_r
|
|
emit_sha1c :: emit_sha1c_r_r_r
|
|
inst_sha1p :: inst_sha1p_r_r_r
|
|
emit_sha1p :: emit_sha1p_r_r_r
|
|
inst_sha1m :: inst_sha1m_r_r_r
|
|
emit_sha1m :: emit_sha1m_r_r_r
|
|
inst_sha1su0 :: inst_sha1su0_r_r_r
|
|
emit_sha1su0 :: emit_sha1su0_r_r_r
|
|
inst_sha1su1 :: inst_sha1su1_r_r
|
|
emit_sha1su1 :: emit_sha1su1_r_r
|
|
inst_sha256h :: inst_sha256h_r_r_r
|
|
emit_sha256h :: emit_sha256h_r_r_r
|
|
inst_sha256h2 :: inst_sha256h2_r_r_r
|
|
emit_sha256h2 :: emit_sha256h2_r_r_r
|
|
inst_sha256su0 :: inst_sha256su0_r_r
|
|
emit_sha256su0 :: emit_sha256su0_r_r
|
|
inst_sha256su1 :: inst_sha256su1_r_r_r
|
|
emit_sha256su1 :: emit_sha256su1_r_r_r
|
|
inst_sha512h :: inst_sha512h_r_r_r
|
|
emit_sha512h :: emit_sha512h_r_r_r
|
|
inst_sha512h2 :: inst_sha512h2_r_r_r
|
|
emit_sha512h2 :: emit_sha512h2_r_r_r
|
|
inst_sha512su0 :: inst_sha512su0_r_r
|
|
emit_sha512su0 :: emit_sha512su0_r_r
|
|
inst_sha512su1 :: inst_sha512su1_r_r_r
|
|
emit_sha512su1 :: emit_sha512su1_r_r_r
|
|
inst_eor3 :: inst_eor3_r_r_r_r
|
|
emit_eor3 :: emit_eor3_r_r_r_r
|
|
inst_bcax :: inst_bcax_r_r_r_r
|
|
emit_bcax :: emit_bcax_r_r_r_r
|
|
inst_rax1 :: inst_rax1_r_r_r
|
|
emit_rax1 :: emit_rax1_r_r_r
|
|
inst_xar :: inst_xar_r_r_r_i
|
|
emit_xar :: emit_xar_r_r_r_i
|
|
inst_sm3partw1 :: inst_sm3partw1_r_r_r
|
|
emit_sm3partw1 :: emit_sm3partw1_r_r_r
|
|
inst_sm3partw2 :: inst_sm3partw2_r_r_r
|
|
emit_sm3partw2 :: emit_sm3partw2_r_r_r
|
|
inst_sm3ss1 :: inst_sm3ss1_r_r_r_r
|
|
emit_sm3ss1 :: emit_sm3ss1_r_r_r_r
|
|
inst_sm3tt1a :: inst_sm3tt1a_r_r_r
|
|
emit_sm3tt1a :: emit_sm3tt1a_r_r_r
|
|
inst_sm3tt1b :: inst_sm3tt1b_r_r_r
|
|
emit_sm3tt1b :: emit_sm3tt1b_r_r_r
|
|
inst_sm3tt2a :: inst_sm3tt2a_r_r_r
|
|
emit_sm3tt2a :: emit_sm3tt2a_r_r_r
|
|
inst_sm3tt2b :: inst_sm3tt2b_r_r_r
|
|
emit_sm3tt2b :: emit_sm3tt2b_r_r_r
|
|
inst_sm4e :: inst_sm4e_r_r
|
|
emit_sm4e :: emit_sm4e_r_r
|
|
inst_sm4ekey :: inst_sm4ekey_r_r_r
|
|
emit_sm4ekey :: emit_sm4ekey_r_r_r
|
|
inst_pmull :: inst_pmull_r_r_r
|
|
emit_pmull :: emit_pmull_r_r_r
|
|
inst_pmull2 :: inst_pmull2_r_r_r
|
|
emit_pmull2 :: emit_pmull2_r_r_r
|
|
inst_fabs_h :: inst_fabs_h_r_r
|
|
emit_fabs_h :: emit_fabs_h_r_r
|
|
inst_fneg_h :: inst_fneg_h_r_r
|
|
emit_fneg_h :: emit_fneg_h_r_r
|
|
inst_fsqrt_h :: inst_fsqrt_h_r_r
|
|
emit_fsqrt_h :: emit_fsqrt_h_r_r
|
|
inst_fadd_h :: inst_fadd_h_r_r_r
|
|
emit_fadd_h :: emit_fadd_h_r_r_r
|
|
inst_fsub_h :: inst_fsub_h_r_r_r
|
|
emit_fsub_h :: emit_fsub_h_r_r_r
|
|
inst_fmul_h :: inst_fmul_h_r_r_r
|
|
emit_fmul_h :: emit_fmul_h_r_r_r
|
|
inst_fdiv_h :: inst_fdiv_h_r_r_r
|
|
emit_fdiv_h :: emit_fdiv_h_r_r_r
|
|
inst_fnmul_h :: inst_fnmul_h_r_r_r
|
|
emit_fnmul_h :: emit_fnmul_h_r_r_r
|
|
inst_fmadd_h :: inst_fmadd_h_r_r_r_r
|
|
emit_fmadd_h :: emit_fmadd_h_r_r_r_r
|
|
inst_fmsub_h :: inst_fmsub_h_r_r_r_r
|
|
emit_fmsub_h :: emit_fmsub_h_r_r_r_r
|
|
inst_fnmadd_h :: inst_fnmadd_h_r_r_r_r
|
|
emit_fnmadd_h :: emit_fnmadd_h_r_r_r_r
|
|
inst_fnmsub_h :: inst_fnmsub_h_r_r_r_r
|
|
emit_fnmsub_h :: emit_fnmsub_h_r_r_r_r
|
|
inst_fcmp_h :: inst_fcmp_h_r_r
|
|
emit_fcmp_h :: emit_fcmp_h_r_r
|
|
inst_fcmpe_h :: inst_fcmpe_h_r_r
|
|
emit_fcmpe_h :: emit_fcmpe_h_r_r
|
|
inst_fcsel_h :: inst_fcsel_h_r_r_r_c
|
|
emit_fcsel_h :: emit_fcsel_h_r_r_r_c
|
|
inst_fmax_h :: inst_fmax_h_r_r_r
|
|
emit_fmax_h :: emit_fmax_h_r_r_r
|
|
inst_fmin_h :: inst_fmin_h_r_r_r
|
|
emit_fmin_h :: emit_fmin_h_r_r_r
|
|
inst_fmaxnm_h :: inst_fmaxnm_h_r_r_r
|
|
emit_fmaxnm_h :: emit_fmaxnm_h_r_r_r
|
|
inst_fminnm_h :: inst_fminnm_h_r_r_r
|
|
emit_fminnm_h :: emit_fminnm_h_r_r_r
|
|
inst_fcvt_h_s :: inst_fcvt_h_s_r_r
|
|
emit_fcvt_h_s :: emit_fcvt_h_s_r_r
|
|
inst_fcvt_h_d :: inst_fcvt_h_d_r_r
|
|
emit_fcvt_h_d :: emit_fcvt_h_d_r_r
|
|
inst_fcvt_s_h :: inst_fcvt_s_h_r_r
|
|
emit_fcvt_s_h :: emit_fcvt_s_h_r_r
|
|
inst_fcvt_d_h :: inst_fcvt_d_h_r_r
|
|
emit_fcvt_d_h :: emit_fcvt_d_h_r_r
|
|
inst_fmov_h :: inst_fmov_h_r_r
|
|
emit_fmov_h :: emit_fmov_h_r_r
|
|
inst_scvtf_h :: inst_scvtf_h_r_r
|
|
emit_scvtf_h :: emit_scvtf_h_r_r
|
|
inst_ucvtf_h :: inst_ucvtf_h_r_r
|
|
emit_ucvtf_h :: emit_ucvtf_h_r_r
|
|
inst_fcvtzs_h :: inst_fcvtzs_h_r_r
|
|
emit_fcvtzs_h :: emit_fcvtzs_h_r_r
|
|
inst_fcvtzu_h :: inst_fcvtzu_h_r_r
|
|
emit_fcvtzu_h :: emit_fcvtzu_h_r_r
|
|
inst_bfcvt :: inst_bfcvt_r_r
|
|
emit_bfcvt :: emit_bfcvt_r_r
|
|
inst_bfdot :: inst_bfdot_r_r_r
|
|
emit_bfdot :: emit_bfdot_r_r_r
|
|
inst_bfmmla :: inst_bfmmla_r_r_r
|
|
emit_bfmmla :: emit_bfmmla_r_r_r
|
|
inst_bfmlalb :: inst_bfmlalb_r_r_r
|
|
emit_bfmlalb :: emit_bfmlalb_r_r_r
|
|
inst_bfmlalt :: inst_bfmlalt_r_r_r
|
|
emit_bfmlalt :: emit_bfmlalt_r_r_r
|
|
inst_bfcvtn :: inst_bfcvtn_r_r
|
|
emit_bfcvtn :: emit_bfcvtn_r_r
|
|
inst_bfcvtn2 :: inst_bfcvtn2_r_r
|
|
emit_bfcvtn2 :: emit_bfcvtn2_r_r
|
|
inst_add_v :: inst_add_v_r_r_r
|
|
emit_add_v :: emit_add_v_r_r_r
|
|
inst_sub_v :: inst_sub_v_r_r_r
|
|
emit_sub_v :: emit_sub_v_r_r_r
|
|
inst_mul_v :: inst_mul_v_r_r_r
|
|
emit_mul_v :: emit_mul_v_r_r_r
|
|
inst_mla_v :: inst_mla_v_r_r_r
|
|
emit_mla_v :: emit_mla_v_r_r_r
|
|
inst_mls_v :: inst_mls_v_r_r_r
|
|
emit_mls_v :: emit_mls_v_r_r_r
|
|
inst_neg_v :: inst_neg_v_r_r
|
|
emit_neg_v :: emit_neg_v_r_r
|
|
inst_abs_v :: inst_abs_v_r_r
|
|
emit_abs_v :: emit_abs_v_r_r
|
|
inst_shadd :: inst_shadd_r_r_r
|
|
emit_shadd :: emit_shadd_r_r_r
|
|
inst_uhadd :: inst_uhadd_r_r_r
|
|
emit_uhadd :: emit_uhadd_r_r_r
|
|
inst_shsub :: inst_shsub_r_r_r
|
|
emit_shsub :: emit_shsub_r_r_r
|
|
inst_uhsub :: inst_uhsub_r_r_r
|
|
emit_uhsub :: emit_uhsub_r_r_r
|
|
inst_srhadd :: inst_srhadd_r_r_r
|
|
emit_srhadd :: emit_srhadd_r_r_r
|
|
inst_urhadd :: inst_urhadd_r_r_r
|
|
emit_urhadd :: emit_urhadd_r_r_r
|
|
inst_sqadd :: inst_sqadd_r_r_r
|
|
emit_sqadd :: emit_sqadd_r_r_r
|
|
inst_uqadd :: inst_uqadd_r_r_r
|
|
emit_uqadd :: emit_uqadd_r_r_r
|
|
inst_sqsub :: inst_sqsub_r_r_r
|
|
emit_sqsub :: emit_sqsub_r_r_r
|
|
inst_uqsub :: inst_uqsub_r_r_r
|
|
emit_uqsub :: emit_uqsub_r_r_r
|
|
inst_smax :: inst_smax_r_r_r
|
|
emit_smax :: emit_smax_r_r_r
|
|
inst_umax :: inst_umax_r_r_r
|
|
emit_umax :: emit_umax_r_r_r
|
|
inst_smin :: inst_smin_r_r_r
|
|
emit_smin :: emit_smin_r_r_r
|
|
inst_umin :: inst_umin_r_r_r
|
|
emit_umin :: emit_umin_r_r_r
|
|
inst_sabd :: inst_sabd_r_r_r
|
|
emit_sabd :: emit_sabd_r_r_r
|
|
inst_uabd :: inst_uabd_r_r_r
|
|
emit_uabd :: emit_uabd_r_r_r
|
|
inst_saba :: inst_saba_r_r_r
|
|
emit_saba :: emit_saba_r_r_r
|
|
inst_uaba :: inst_uaba_r_r_r
|
|
emit_uaba :: emit_uaba_r_r_r
|
|
inst_addp_v :: inst_addp_v_r_r_r
|
|
emit_addp_v :: emit_addp_v_r_r_r
|
|
inst_addv :: inst_addv_r_r
|
|
emit_addv :: emit_addv_r_r
|
|
inst_saddlp :: inst_saddlp_r_r
|
|
emit_saddlp :: emit_saddlp_r_r
|
|
inst_uaddlp :: inst_uaddlp_r_r
|
|
emit_uaddlp :: emit_uaddlp_r_r
|
|
inst_sadalp :: inst_sadalp_r_r
|
|
emit_sadalp :: emit_sadalp_r_r
|
|
inst_uadalp :: inst_uadalp_r_r
|
|
emit_uadalp :: emit_uadalp_r_r
|
|
inst_saddlv :: inst_saddlv_r_r
|
|
emit_saddlv :: emit_saddlv_r_r
|
|
inst_uaddlv :: inst_uaddlv_r_r
|
|
emit_uaddlv :: emit_uaddlv_r_r
|
|
inst_smaxv :: inst_smaxv_r_r
|
|
emit_smaxv :: emit_smaxv_r_r
|
|
inst_umaxv :: inst_umaxv_r_r
|
|
emit_umaxv :: emit_umaxv_r_r
|
|
inst_sminv :: inst_sminv_r_r
|
|
emit_sminv :: emit_sminv_r_r
|
|
inst_uminv :: inst_uminv_r_r
|
|
emit_uminv :: emit_uminv_r_r
|
|
inst_smaxp :: inst_smaxp_r_r_r
|
|
emit_smaxp :: emit_smaxp_r_r_r
|
|
inst_umaxp :: inst_umaxp_r_r_r
|
|
emit_umaxp :: emit_umaxp_r_r_r
|
|
inst_sminp :: inst_sminp_r_r_r
|
|
emit_sminp :: emit_sminp_r_r_r
|
|
inst_uminp :: inst_uminp_r_r_r
|
|
emit_uminp :: emit_uminp_r_r_r
|
|
inst_saddl :: inst_saddl_r_r_r
|
|
emit_saddl :: emit_saddl_r_r_r
|
|
inst_saddl2 :: inst_saddl2_r_r_r
|
|
emit_saddl2 :: emit_saddl2_r_r_r
|
|
inst_uaddl :: inst_uaddl_r_r_r
|
|
emit_uaddl :: emit_uaddl_r_r_r
|
|
inst_uaddl2 :: inst_uaddl2_r_r_r
|
|
emit_uaddl2 :: emit_uaddl2_r_r_r
|
|
inst_ssubl :: inst_ssubl_r_r_r
|
|
emit_ssubl :: emit_ssubl_r_r_r
|
|
inst_ssubl2 :: inst_ssubl2_r_r_r
|
|
emit_ssubl2 :: emit_ssubl2_r_r_r
|
|
inst_usubl :: inst_usubl_r_r_r
|
|
emit_usubl :: emit_usubl_r_r_r
|
|
inst_usubl2 :: inst_usubl2_r_r_r
|
|
emit_usubl2 :: emit_usubl2_r_r_r
|
|
inst_saddw :: inst_saddw_r_r_r
|
|
emit_saddw :: emit_saddw_r_r_r
|
|
inst_saddw2 :: inst_saddw2_r_r_r
|
|
emit_saddw2 :: emit_saddw2_r_r_r
|
|
inst_uaddw :: inst_uaddw_r_r_r
|
|
emit_uaddw :: emit_uaddw_r_r_r
|
|
inst_uaddw2 :: inst_uaddw2_r_r_r
|
|
emit_uaddw2 :: emit_uaddw2_r_r_r
|
|
inst_ssubw :: inst_ssubw_r_r_r
|
|
emit_ssubw :: emit_ssubw_r_r_r
|
|
inst_ssubw2 :: inst_ssubw2_r_r_r
|
|
emit_ssubw2 :: emit_ssubw2_r_r_r
|
|
inst_usubw :: inst_usubw_r_r_r
|
|
emit_usubw :: emit_usubw_r_r_r
|
|
inst_usubw2 :: inst_usubw2_r_r_r
|
|
emit_usubw2 :: emit_usubw2_r_r_r
|
|
inst_raddhn :: inst_raddhn_r_r_r
|
|
emit_raddhn :: emit_raddhn_r_r_r
|
|
inst_raddhn2 :: inst_raddhn2_r_r_r
|
|
emit_raddhn2 :: emit_raddhn2_r_r_r
|
|
inst_rsubhn :: inst_rsubhn_r_r_r
|
|
emit_rsubhn :: emit_rsubhn_r_r_r
|
|
inst_rsubhn2 :: inst_rsubhn2_r_r_r
|
|
emit_rsubhn2 :: emit_rsubhn2_r_r_r
|
|
inst_addhn :: inst_addhn_r_r_r
|
|
emit_addhn :: emit_addhn_r_r_r
|
|
inst_addhn2 :: inst_addhn2_r_r_r
|
|
emit_addhn2 :: emit_addhn2_r_r_r
|
|
inst_subhn :: inst_subhn_r_r_r
|
|
emit_subhn :: emit_subhn_r_r_r
|
|
inst_subhn2 :: inst_subhn2_r_r_r
|
|
emit_subhn2 :: emit_subhn2_r_r_r
|
|
inst_xtn :: inst_xtn_r_r
|
|
emit_xtn :: emit_xtn_r_r
|
|
inst_xtn2 :: inst_xtn2_r_r
|
|
emit_xtn2 :: emit_xtn2_r_r
|
|
inst_sqxtn :: inst_sqxtn_r_r
|
|
emit_sqxtn :: emit_sqxtn_r_r
|
|
inst_sqxtn2 :: inst_sqxtn2_r_r
|
|
emit_sqxtn2 :: emit_sqxtn2_r_r
|
|
inst_uqxtn :: inst_uqxtn_r_r
|
|
emit_uqxtn :: emit_uqxtn_r_r
|
|
inst_uqxtn2 :: inst_uqxtn2_r_r
|
|
emit_uqxtn2 :: emit_uqxtn2_r_r
|
|
inst_sqxtun :: inst_sqxtun_r_r
|
|
emit_sqxtun :: emit_sqxtun_r_r
|
|
inst_sqxtun2 :: inst_sqxtun2_r_r
|
|
emit_sqxtun2 :: emit_sqxtun2_r_r
|
|
inst_smull_v :: inst_smull_v_r_r_r
|
|
emit_smull_v :: emit_smull_v_r_r_r
|
|
inst_smull2_v :: inst_smull2_v_r_r_r
|
|
emit_smull2_v :: emit_smull2_v_r_r_r
|
|
inst_umull_v :: inst_umull_v_r_r_r
|
|
emit_umull_v :: emit_umull_v_r_r_r
|
|
inst_umull2_v :: inst_umull2_v_r_r_r
|
|
emit_umull2_v :: emit_umull2_v_r_r_r
|
|
inst_smlal :: inst_smlal_r_r_r
|
|
emit_smlal :: emit_smlal_r_r_r
|
|
inst_smlal2 :: inst_smlal2_r_r_r
|
|
emit_smlal2 :: emit_smlal2_r_r_r
|
|
inst_umlal :: inst_umlal_r_r_r
|
|
emit_umlal :: emit_umlal_r_r_r
|
|
inst_umlal2 :: inst_umlal2_r_r_r
|
|
emit_umlal2 :: emit_umlal2_r_r_r
|
|
inst_smlsl :: inst_smlsl_r_r_r
|
|
emit_smlsl :: emit_smlsl_r_r_r
|
|
inst_smlsl2 :: inst_smlsl2_r_r_r
|
|
emit_smlsl2 :: emit_smlsl2_r_r_r
|
|
inst_umlsl :: inst_umlsl_r_r_r
|
|
emit_umlsl :: emit_umlsl_r_r_r
|
|
inst_umlsl2 :: inst_umlsl2_r_r_r
|
|
emit_umlsl2 :: emit_umlsl2_r_r_r
|
|
inst_sqdmull :: inst_sqdmull_r_r_r
|
|
emit_sqdmull :: emit_sqdmull_r_r_r
|
|
inst_sqdmull2 :: inst_sqdmull2_r_r_r
|
|
emit_sqdmull2 :: emit_sqdmull2_r_r_r
|
|
inst_sqdmlal :: inst_sqdmlal_r_r_r
|
|
emit_sqdmlal :: emit_sqdmlal_r_r_r
|
|
inst_sqdmlal2 :: inst_sqdmlal2_r_r_r
|
|
emit_sqdmlal2 :: emit_sqdmlal2_r_r_r
|
|
inst_sqdmlsl :: inst_sqdmlsl_r_r_r
|
|
emit_sqdmlsl :: emit_sqdmlsl_r_r_r
|
|
inst_sqdmlsl2 :: inst_sqdmlsl2_r_r_r
|
|
emit_sqdmlsl2 :: emit_sqdmlsl2_r_r_r
|
|
inst_sqdmulh :: inst_sqdmulh_r_r_r
|
|
emit_sqdmulh :: emit_sqdmulh_r_r_r
|
|
inst_sqrdmulh :: inst_sqrdmulh_r_r_r
|
|
emit_sqrdmulh :: emit_sqrdmulh_r_r_r
|
|
inst_sdot :: inst_sdot_r_r_r
|
|
emit_sdot :: emit_sdot_r_r_r
|
|
inst_udot :: inst_udot_r_r_r
|
|
emit_udot :: emit_udot_r_r_r
|
|
inst_usdot :: inst_usdot_r_r_r
|
|
emit_usdot :: emit_usdot_r_r_r
|
|
inst_fadd_v :: inst_fadd_v_r_r_r
|
|
emit_fadd_v :: emit_fadd_v_r_r_r
|
|
inst_fsub_v :: inst_fsub_v_r_r_r
|
|
emit_fsub_v :: emit_fsub_v_r_r_r
|
|
inst_fmul_v :: inst_fmul_v_r_r_r
|
|
emit_fmul_v :: emit_fmul_v_r_r_r
|
|
inst_fdiv_v :: inst_fdiv_v_r_r_r
|
|
emit_fdiv_v :: emit_fdiv_v_r_r_r
|
|
inst_fneg_v :: inst_fneg_v_r_r
|
|
emit_fneg_v :: emit_fneg_v_r_r
|
|
inst_fabs_v :: inst_fabs_v_r_r
|
|
emit_fabs_v :: emit_fabs_v_r_r
|
|
inst_fsqrt_v :: inst_fsqrt_v_r_r
|
|
emit_fsqrt_v :: emit_fsqrt_v_r_r
|
|
inst_fmla_v :: inst_fmla_v_r_r_r
|
|
emit_fmla_v :: emit_fmla_v_r_r_r
|
|
inst_fmls_v :: inst_fmls_v_r_r_r
|
|
emit_fmls_v :: emit_fmls_v_r_r_r
|
|
inst_fmulx :: inst_fmulx_r_r_r
|
|
emit_fmulx :: emit_fmulx_r_r_r
|
|
inst_fmax_v :: inst_fmax_v_r_r_r
|
|
emit_fmax_v :: emit_fmax_v_r_r_r
|
|
inst_fmin_v :: inst_fmin_v_r_r_r
|
|
emit_fmin_v :: emit_fmin_v_r_r_r
|
|
inst_fmaxnm_v :: inst_fmaxnm_v_r_r_r
|
|
emit_fmaxnm_v :: emit_fmaxnm_v_r_r_r
|
|
inst_fminnm_v :: inst_fminnm_v_r_r_r
|
|
emit_fminnm_v :: emit_fminnm_v_r_r_r
|
|
inst_fmaxp_v :: inst_fmaxp_v_r_r_r
|
|
emit_fmaxp_v :: emit_fmaxp_v_r_r_r
|
|
inst_fminp_v :: inst_fminp_v_r_r_r
|
|
emit_fminp_v :: emit_fminp_v_r_r_r
|
|
inst_fmaxnmp :: inst_fmaxnmp_r_r_r
|
|
emit_fmaxnmp :: emit_fmaxnmp_r_r_r
|
|
inst_fminnmp :: inst_fminnmp_r_r_r
|
|
emit_fminnmp :: emit_fminnmp_r_r_r
|
|
inst_fmaxv_v :: inst_fmaxv_v_r_r
|
|
emit_fmaxv_v :: emit_fmaxv_v_r_r
|
|
inst_fminv_v :: inst_fminv_v_r_r
|
|
emit_fminv_v :: emit_fminv_v_r_r
|
|
inst_fmaxnmv :: inst_fmaxnmv_r_r
|
|
emit_fmaxnmv :: emit_fmaxnmv_r_r
|
|
inst_fminnmv :: inst_fminnmv_r_r
|
|
emit_fminnmv :: emit_fminnmv_r_r
|
|
inst_frecpe :: inst_frecpe_r_r
|
|
emit_frecpe :: emit_frecpe_r_r
|
|
inst_frsqrte :: inst_frsqrte_r_r
|
|
emit_frsqrte :: emit_frsqrte_r_r
|
|
inst_frecps :: inst_frecps_r_r_r
|
|
emit_frecps :: emit_frecps_r_r_r
|
|
inst_frsqrts :: inst_frsqrts_r_r_r
|
|
emit_frsqrts :: emit_frsqrts_r_r_r
|
|
inst_frecpx :: inst_frecpx_r_r
|
|
emit_frecpx :: emit_frecpx_r_r
|
|
inst_faddp_v :: inst_faddp_v_r_r_r
|
|
emit_faddp_v :: emit_faddp_v_r_r_r
|
|
inst_frinta_v :: inst_frinta_v_r_r
|
|
emit_frinta_v :: emit_frinta_v_r_r
|
|
inst_frinti_v :: inst_frinti_v_r_r
|
|
emit_frinti_v :: emit_frinti_v_r_r
|
|
inst_frintm_v :: inst_frintm_v_r_r
|
|
emit_frintm_v :: emit_frintm_v_r_r
|
|
inst_frintn_v :: inst_frintn_v_r_r
|
|
emit_frintn_v :: emit_frintn_v_r_r
|
|
inst_frintp_v :: inst_frintp_v_r_r
|
|
emit_frintp_v :: emit_frintp_v_r_r
|
|
inst_frintx_v :: inst_frintx_v_r_r
|
|
emit_frintx_v :: emit_frintx_v_r_r
|
|
inst_frintz_v :: inst_frintz_v_r_r
|
|
emit_frintz_v :: emit_frintz_v_r_r
|
|
inst_scvtf_v :: inst_scvtf_v_r_r
|
|
emit_scvtf_v :: emit_scvtf_v_r_r
|
|
inst_ucvtf_v :: inst_ucvtf_v_r_r
|
|
emit_ucvtf_v :: emit_ucvtf_v_r_r
|
|
inst_fcvtas_v :: inst_fcvtas_v_r_r
|
|
emit_fcvtas_v :: emit_fcvtas_v_r_r
|
|
inst_fcvtau_v :: inst_fcvtau_v_r_r
|
|
emit_fcvtau_v :: emit_fcvtau_v_r_r
|
|
inst_fcvtms_v :: inst_fcvtms_v_r_r
|
|
emit_fcvtms_v :: emit_fcvtms_v_r_r
|
|
inst_fcvtmu_v :: inst_fcvtmu_v_r_r
|
|
emit_fcvtmu_v :: emit_fcvtmu_v_r_r
|
|
inst_fcvtns_v :: inst_fcvtns_v_r_r
|
|
emit_fcvtns_v :: emit_fcvtns_v_r_r
|
|
inst_fcvtnu_v :: inst_fcvtnu_v_r_r
|
|
emit_fcvtnu_v :: emit_fcvtnu_v_r_r
|
|
inst_fcvtps_v :: inst_fcvtps_v_r_r
|
|
emit_fcvtps_v :: emit_fcvtps_v_r_r
|
|
inst_fcvtpu_v :: inst_fcvtpu_v_r_r
|
|
emit_fcvtpu_v :: emit_fcvtpu_v_r_r
|
|
inst_fcvtzs_v :: inst_fcvtzs_v_r_r
|
|
emit_fcvtzs_v :: emit_fcvtzs_v_r_r
|
|
inst_fcvtzu_v :: inst_fcvtzu_v_r_r
|
|
emit_fcvtzu_v :: emit_fcvtzu_v_r_r
|
|
inst_fcvtl :: inst_fcvtl_r_r
|
|
emit_fcvtl :: emit_fcvtl_r_r
|
|
inst_fcvtl2 :: inst_fcvtl2_r_r
|
|
emit_fcvtl2 :: emit_fcvtl2_r_r
|
|
inst_fcvtn :: inst_fcvtn_r_r
|
|
emit_fcvtn :: emit_fcvtn_r_r
|
|
inst_fcvtn2 :: inst_fcvtn2_r_r
|
|
emit_fcvtn2 :: emit_fcvtn2_r_r
|
|
inst_fcvtxn :: inst_fcvtxn_r_r
|
|
emit_fcvtxn :: emit_fcvtxn_r_r
|
|
inst_fcvtxn2 :: inst_fcvtxn2_r_r
|
|
emit_fcvtxn2 :: emit_fcvtxn2_r_r
|
|
inst_fcmeq :: inst_fcmeq_r_r_r
|
|
emit_fcmeq :: emit_fcmeq_r_r_r
|
|
inst_fcmge :: inst_fcmge_r_r_r
|
|
emit_fcmge :: emit_fcmge_r_r_r
|
|
inst_fcmgt :: inst_fcmgt_r_r_r
|
|
emit_fcmgt :: emit_fcmgt_r_r_r
|
|
inst_fcmle :: inst_fcmle_r_r
|
|
emit_fcmle :: emit_fcmle_r_r
|
|
inst_fcmlt :: inst_fcmlt_r_r
|
|
emit_fcmlt :: emit_fcmlt_r_r
|
|
inst_facge :: inst_facge_r_r_r
|
|
emit_facge :: emit_facge_r_r_r
|
|
inst_facgt :: inst_facgt_r_r_r
|
|
emit_facgt :: emit_facgt_r_r_r
|
|
inst_cmeq :: inst_cmeq_r_r_r
|
|
emit_cmeq :: emit_cmeq_r_r_r
|
|
inst_cmge :: inst_cmge_r_r_r
|
|
emit_cmge :: emit_cmge_r_r_r
|
|
inst_cmgt :: inst_cmgt_r_r_r
|
|
emit_cmgt :: emit_cmgt_r_r_r
|
|
inst_cmhi :: inst_cmhi_r_r_r
|
|
emit_cmhi :: emit_cmhi_r_r_r
|
|
inst_cmhs :: inst_cmhs_r_r_r
|
|
emit_cmhs :: emit_cmhs_r_r_r
|
|
inst_cmle :: inst_cmle_r_r
|
|
emit_cmle :: emit_cmle_r_r
|
|
inst_cmlt :: inst_cmlt_r_r
|
|
emit_cmlt :: emit_cmlt_r_r
|
|
inst_cmtst :: inst_cmtst_r_r_r
|
|
emit_cmtst :: emit_cmtst_r_r_r
|
|
inst_and_v :: inst_and_v_r_r_r
|
|
emit_and_v :: emit_and_v_r_r_r
|
|
inst_orr_v :: inst_orr_v_r_r_r
|
|
emit_orr_v :: emit_orr_v_r_r_r
|
|
inst_eor_v :: inst_eor_v_r_r_r
|
|
emit_eor_v :: emit_eor_v_r_r_r
|
|
inst_bic_v :: inst_bic_v_r_r_r
|
|
emit_bic_v :: emit_bic_v_r_r_r
|
|
inst_orn_v :: inst_orn_v_r_r_r
|
|
emit_orn_v :: emit_orn_v_r_r_r
|
|
inst_mvn_v :: inst_mvn_v_r_r
|
|
emit_mvn_v :: emit_mvn_v_r_r
|
|
inst_bit :: inst_bit_r_r_r
|
|
emit_bit :: emit_bit_r_r_r
|
|
inst_bif :: inst_bif_r_r_r
|
|
emit_bif :: emit_bif_r_r_r
|
|
inst_bsl :: inst_bsl_r_r_r
|
|
emit_bsl :: emit_bsl_r_r_r
|
|
inst_shl_v :: inst_shl_v_r_r_i
|
|
emit_shl_v :: emit_shl_v_r_r_i
|
|
inst_sqshl_v :: inst_sqshl_v_r_r_i
|
|
emit_sqshl_v :: emit_sqshl_v_r_r_i
|
|
inst_sqshlu :: inst_sqshlu_r_r_i
|
|
emit_sqshlu :: emit_sqshlu_r_r_i
|
|
inst_srshl :: inst_srshl_r_r_r
|
|
emit_srshl :: emit_srshl_r_r_r
|
|
inst_urshl :: inst_urshl_r_r_r
|
|
emit_urshl :: emit_urshl_r_r_r
|
|
inst_sshr :: inst_sshr_r_r_i
|
|
emit_sshr :: emit_sshr_r_r_i
|
|
inst_ushr :: inst_ushr_r_r_i
|
|
emit_ushr :: emit_ushr_r_r_i
|
|
inst_ssra :: inst_ssra_r_r_i
|
|
emit_ssra :: emit_ssra_r_r_i
|
|
inst_usra :: inst_usra_r_r_i
|
|
emit_usra :: emit_usra_r_r_i
|
|
inst_srshr :: inst_srshr_r_r_i
|
|
emit_srshr :: emit_srshr_r_r_i
|
|
inst_urshr :: inst_urshr_r_r_i
|
|
emit_urshr :: emit_urshr_r_r_i
|
|
inst_srsra :: inst_srsra_r_r_i
|
|
emit_srsra :: emit_srsra_r_r_i
|
|
inst_ursra :: inst_ursra_r_r_i
|
|
emit_ursra :: emit_ursra_r_r_i
|
|
inst_sshl :: inst_sshl_r_r_r
|
|
emit_sshl :: emit_sshl_r_r_r
|
|
inst_ushl :: inst_ushl_r_r_r
|
|
emit_ushl :: emit_ushl_r_r_r
|
|
inst_sli :: inst_sli_r_r_i
|
|
emit_sli :: emit_sli_r_r_i
|
|
inst_sri :: inst_sri_r_r_i
|
|
emit_sri :: emit_sri_r_r_i
|
|
inst_sshll :: inst_sshll_r_r_i
|
|
emit_sshll :: emit_sshll_r_r_i
|
|
inst_sshll2 :: inst_sshll2_r_r_i
|
|
emit_sshll2 :: emit_sshll2_r_r_i
|
|
inst_ushll :: inst_ushll_r_r_i
|
|
emit_ushll :: emit_ushll_r_r_i
|
|
inst_ushll2 :: inst_ushll2_r_r_i
|
|
emit_ushll2 :: emit_ushll2_r_r_i
|
|
inst_sxtl :: inst_sxtl_r_r
|
|
emit_sxtl :: emit_sxtl_r_r
|
|
inst_sxtl2 :: inst_sxtl2_r_r
|
|
emit_sxtl2 :: emit_sxtl2_r_r
|
|
inst_uxtl :: inst_uxtl_r_r
|
|
emit_uxtl :: emit_uxtl_r_r
|
|
inst_uxtl2 :: inst_uxtl2_r_r
|
|
emit_uxtl2 :: emit_uxtl2_r_r
|
|
inst_shrn :: inst_shrn_r_r_i
|
|
emit_shrn :: emit_shrn_r_r_i
|
|
inst_shrn2 :: inst_shrn2_r_r_i
|
|
emit_shrn2 :: emit_shrn2_r_r_i
|
|
inst_rshrn :: inst_rshrn_r_r_i
|
|
emit_rshrn :: emit_rshrn_r_r_i
|
|
inst_rshrn2 :: inst_rshrn2_r_r_i
|
|
emit_rshrn2 :: emit_rshrn2_r_r_i
|
|
inst_sqshrn :: inst_sqshrn_r_r_i
|
|
emit_sqshrn :: emit_sqshrn_r_r_i
|
|
inst_sqshrn2 :: inst_sqshrn2_r_r_i
|
|
emit_sqshrn2 :: emit_sqshrn2_r_r_i
|
|
inst_uqshrn :: inst_uqshrn_r_r_i
|
|
emit_uqshrn :: emit_uqshrn_r_r_i
|
|
inst_uqshrn2 :: inst_uqshrn2_r_r_i
|
|
emit_uqshrn2 :: emit_uqshrn2_r_r_i
|
|
inst_sqrshrn :: inst_sqrshrn_r_r_i
|
|
emit_sqrshrn :: emit_sqrshrn_r_r_i
|
|
inst_sqrshrn2 :: inst_sqrshrn2_r_r_i
|
|
emit_sqrshrn2 :: emit_sqrshrn2_r_r_i
|
|
inst_uqrshrn :: inst_uqrshrn_r_r_i
|
|
emit_uqrshrn :: emit_uqrshrn_r_r_i
|
|
inst_uqrshrn2 :: inst_uqrshrn2_r_r_i
|
|
emit_uqrshrn2 :: emit_uqrshrn2_r_r_i
|
|
inst_sqshrun :: inst_sqshrun_r_r_i
|
|
emit_sqshrun :: emit_sqshrun_r_r_i
|
|
inst_sqshrun2 :: inst_sqshrun2_r_r_i
|
|
emit_sqshrun2 :: emit_sqshrun2_r_r_i
|
|
inst_sqrshrun :: inst_sqrshrun_r_r_i
|
|
emit_sqrshrun :: emit_sqrshrun_r_r_i
|
|
inst_sqrshrun2 :: inst_sqrshrun2_r_r_i
|
|
emit_sqrshrun2 :: emit_sqrshrun2_r_r_i
|
|
inst_dup_v :: proc{ inst_dup_v_r_r_i, inst_dup_v_r_r }
|
|
emit_dup_v :: proc{ emit_dup_v_r_r_i, emit_dup_v_r_r }
|
|
inst_ins :: proc{ inst_ins_r_i_r_i, inst_ins_r_i_r }
|
|
emit_ins :: proc{ emit_ins_r_i_r_i, emit_ins_r_i_r }
|
|
inst_mov_v :: inst_mov_v_r_r
|
|
emit_mov_v :: emit_mov_v_r_r
|
|
inst_ext_v :: inst_ext_v_r_r_r_i
|
|
emit_ext_v :: emit_ext_v_r_r_r_i
|
|
inst_tbl :: inst_tbl_r_r_r
|
|
emit_tbl :: emit_tbl_r_r_r
|
|
inst_tbx :: inst_tbx_r_r_r
|
|
emit_tbx :: emit_tbx_r_r_r
|
|
inst_zip1 :: inst_zip1_r_r_r
|
|
emit_zip1 :: emit_zip1_r_r_r
|
|
inst_zip2 :: inst_zip2_r_r_r
|
|
emit_zip2 :: emit_zip2_r_r_r
|
|
inst_uzp1 :: inst_uzp1_r_r_r
|
|
emit_uzp1 :: emit_uzp1_r_r_r
|
|
inst_uzp2 :: inst_uzp2_r_r_r
|
|
emit_uzp2 :: emit_uzp2_r_r_r
|
|
inst_trn1 :: inst_trn1_r_r_r
|
|
emit_trn1 :: emit_trn1_r_r_r
|
|
inst_trn2 :: inst_trn2_r_r_r
|
|
emit_trn2 :: emit_trn2_r_r_r
|
|
inst_not_v :: inst_not_v_r_r
|
|
emit_not_v :: emit_not_v_r_r
|
|
inst_rbit_v :: inst_rbit_v_r_r
|
|
emit_rbit_v :: emit_rbit_v_r_r
|
|
inst_rev16_v :: inst_rev16_v_r_r
|
|
emit_rev16_v :: emit_rev16_v_r_r
|
|
inst_rev32_v :: inst_rev32_v_r_r
|
|
emit_rev32_v :: emit_rev32_v_r_r
|
|
inst_rev64 :: inst_rev64_r_r
|
|
emit_rev64 :: emit_rev64_r_r
|
|
inst_cls_v :: inst_cls_v_r_r
|
|
emit_cls_v :: emit_cls_v_r_r
|
|
inst_clz_v :: inst_clz_v_r_r
|
|
emit_clz_v :: emit_clz_v_r_r
|
|
inst_cnt :: inst_cnt_r_r
|
|
emit_cnt :: emit_cnt_r_r
|
|
inst_urecpe_v :: inst_urecpe_v_r_r
|
|
emit_urecpe_v :: emit_urecpe_v_r_r
|
|
inst_ursqrte_v :: inst_ursqrte_v_r_r
|
|
emit_ursqrte_v :: emit_ursqrte_v_r_r
|
|
inst_movi :: inst_movi_r_i
|
|
emit_movi :: emit_movi_r_i
|
|
inst_mvni :: inst_mvni_r_i
|
|
emit_mvni :: emit_mvni_r_i
|
|
inst_fmov_v_imm :: inst_fmov_v_imm_r_i
|
|
emit_fmov_v_imm :: emit_fmov_v_imm_r_i
|
|
inst_ld1 :: inst_ld1_r_m
|
|
emit_ld1 :: emit_ld1_r_m
|
|
inst_ld2 :: inst_ld2_r_m
|
|
emit_ld2 :: emit_ld2_r_m
|
|
inst_ld3 :: inst_ld3_r_m
|
|
emit_ld3 :: emit_ld3_r_m
|
|
inst_ld4 :: inst_ld4_r_m
|
|
emit_ld4 :: emit_ld4_r_m
|
|
inst_st1 :: inst_st1_r_m
|
|
emit_st1 :: emit_st1_r_m
|
|
inst_st2 :: inst_st2_r_m
|
|
emit_st2 :: emit_st2_r_m
|
|
inst_st3 :: inst_st3_r_m
|
|
emit_st3 :: emit_st3_r_m
|
|
inst_st4 :: inst_st4_r_m
|
|
emit_st4 :: emit_st4_r_m
|
|
inst_ld1r :: inst_ld1r_r_m
|
|
emit_ld1r :: emit_ld1r_r_m
|
|
inst_ld2r :: inst_ld2r_r_m
|
|
emit_ld2r :: emit_ld2r_r_m
|
|
inst_ld3r :: inst_ld3r_r_m
|
|
emit_ld3r :: emit_ld3r_r_m
|
|
inst_ld4r :: inst_ld4r_r_m
|
|
emit_ld4r :: emit_ld4r_r_m
|
|
inst_ld1_lane :: inst_ld1_lane_r_i_m
|
|
emit_ld1_lane :: emit_ld1_lane_r_i_m
|
|
inst_ld2_lane :: inst_ld2_lane_r_i_m
|
|
emit_ld2_lane :: emit_ld2_lane_r_i_m
|
|
inst_ld3_lane :: inst_ld3_lane_r_i_m
|
|
emit_ld3_lane :: emit_ld3_lane_r_i_m
|
|
inst_ld4_lane :: inst_ld4_lane_r_i_m
|
|
emit_ld4_lane :: emit_ld4_lane_r_i_m
|
|
inst_st1_lane :: inst_st1_lane_r_i_m
|
|
emit_st1_lane :: emit_st1_lane_r_i_m
|
|
inst_st2_lane :: inst_st2_lane_r_i_m
|
|
emit_st2_lane :: emit_st2_lane_r_i_m
|
|
inst_st3_lane :: inst_st3_lane_r_i_m
|
|
emit_st3_lane :: emit_st3_lane_r_i_m
|
|
inst_st4_lane :: inst_st4_lane_r_i_m
|
|
emit_st4_lane :: emit_st4_lane_r_i_m
|
|
inst_ldr_v :: inst_ldr_v_r_m
|
|
emit_ldr_v :: emit_ldr_v_r_m
|
|
inst_str_v :: inst_str_v_r_m
|
|
emit_str_v :: emit_str_v_r_m
|
|
inst_ldp_v :: inst_ldp_v_r_r_m
|
|
emit_ldp_v :: emit_ldp_v_r_r_m
|
|
inst_stp_v :: inst_stp_v_r_r_m
|
|
emit_stp_v :: emit_stp_v_r_r_m
|
|
inst_ldur_v :: inst_ldur_v_r_m
|
|
emit_ldur_v :: emit_ldur_v_r_m
|
|
inst_stur_v :: inst_stur_v_r_m
|
|
emit_stur_v :: emit_stur_v_r_m
|
|
inst_sve_add_z :: inst_sve_add_z_z_z_z
|
|
emit_sve_add_z :: emit_sve_add_z_z_z_z
|
|
inst_sve_sub_z :: inst_sve_sub_z_z_z_z
|
|
emit_sve_sub_z :: emit_sve_sub_z_z_z_z
|
|
inst_sve_sqadd_z :: inst_sve_sqadd_z_z_z_z
|
|
emit_sve_sqadd_z :: emit_sve_sqadd_z_z_z_z
|
|
inst_sve_uqadd_z :: inst_sve_uqadd_z_z_z_z
|
|
emit_sve_uqadd_z :: emit_sve_uqadd_z_z_z_z
|
|
inst_sve_sqsub_z :: inst_sve_sqsub_z_z_z_z
|
|
emit_sve_sqsub_z :: emit_sve_sqsub_z_z_z_z
|
|
inst_sve_uqsub_z :: inst_sve_uqsub_z_z_z_z
|
|
emit_sve_uqsub_z :: emit_sve_uqsub_z_z_z_z
|
|
inst_sve_add_pred :: inst_sve_add_pred_z_p_z_z
|
|
emit_sve_add_pred :: emit_sve_add_pred_z_p_z_z
|
|
inst_sve_sub_pred :: inst_sve_sub_pred_z_p_z_z
|
|
emit_sve_sub_pred :: emit_sve_sub_pred_z_p_z_z
|
|
inst_sve_subr_pred :: inst_sve_subr_pred_z_p_z_z
|
|
emit_sve_subr_pred :: emit_sve_subr_pred_z_p_z_z
|
|
inst_sve_mul_pred :: inst_sve_mul_pred_z_p_z_z
|
|
emit_sve_mul_pred :: emit_sve_mul_pred_z_p_z_z
|
|
inst_sve_smulh_pred :: inst_sve_smulh_pred_z_p_z_z
|
|
emit_sve_smulh_pred :: emit_sve_smulh_pred_z_p_z_z
|
|
inst_sve_umulh_pred :: inst_sve_umulh_pred_z_p_z_z
|
|
emit_sve_umulh_pred :: emit_sve_umulh_pred_z_p_z_z
|
|
inst_sve_sdiv_pred :: inst_sve_sdiv_pred_z_p_z_z
|
|
emit_sve_sdiv_pred :: emit_sve_sdiv_pred_z_p_z_z
|
|
inst_sve_udiv_pred :: inst_sve_udiv_pred_z_p_z_z
|
|
emit_sve_udiv_pred :: emit_sve_udiv_pred_z_p_z_z
|
|
inst_sve_smax_pred :: inst_sve_smax_pred_z_p_z_z
|
|
emit_sve_smax_pred :: emit_sve_smax_pred_z_p_z_z
|
|
inst_sve_umax_pred :: inst_sve_umax_pred_z_p_z_z
|
|
emit_sve_umax_pred :: emit_sve_umax_pred_z_p_z_z
|
|
inst_sve_smin_pred :: inst_sve_smin_pred_z_p_z_z
|
|
emit_sve_smin_pred :: emit_sve_smin_pred_z_p_z_z
|
|
inst_sve_umin_pred :: inst_sve_umin_pred_z_p_z_z
|
|
emit_sve_umin_pred :: emit_sve_umin_pred_z_p_z_z
|
|
inst_sve_sabd_pred :: inst_sve_sabd_pred_z_p_z_z
|
|
emit_sve_sabd_pred :: emit_sve_sabd_pred_z_p_z_z
|
|
inst_sve_uabd_pred :: inst_sve_uabd_pred_z_p_z_z
|
|
emit_sve_uabd_pred :: emit_sve_uabd_pred_z_p_z_z
|
|
inst_sve_and_pred :: inst_sve_and_pred_z_p_z_z
|
|
emit_sve_and_pred :: emit_sve_and_pred_z_p_z_z
|
|
inst_sve_orr_pred :: inst_sve_orr_pred_z_p_z_z
|
|
emit_sve_orr_pred :: emit_sve_orr_pred_z_p_z_z
|
|
inst_sve_eor_pred :: inst_sve_eor_pred_z_p_z_z
|
|
emit_sve_eor_pred :: emit_sve_eor_pred_z_p_z_z
|
|
inst_sve_bic_pred :: inst_sve_bic_pred_z_p_z_z
|
|
emit_sve_bic_pred :: emit_sve_bic_pred_z_p_z_z
|
|
inst_sve_asr_pred :: inst_sve_asr_pred_z_p_z_z
|
|
emit_sve_asr_pred :: emit_sve_asr_pred_z_p_z_z
|
|
inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z
|
|
emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z
|
|
inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z
|
|
emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z
|
|
inst_sve_asrr_pred :: inst_sve_asrr_pred_z_p_z_z
|
|
emit_sve_asrr_pred :: emit_sve_asrr_pred_z_p_z_z
|
|
inst_sve_lslr_pred :: inst_sve_lslr_pred_z_p_z_z
|
|
emit_sve_lslr_pred :: emit_sve_lslr_pred_z_p_z_z
|
|
inst_sve_lsrr_pred :: inst_sve_lsrr_pred_z_p_z_z
|
|
emit_sve_lsrr_pred :: emit_sve_lsrr_pred_z_p_z_z
|
|
inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z
|
|
emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z
|
|
inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z
|
|
emit_sve_neg_pred :: emit_sve_neg_pred_z_p_z
|
|
inst_sve_cls_pred :: inst_sve_cls_pred_z_p_z
|
|
emit_sve_cls_pred :: emit_sve_cls_pred_z_p_z
|
|
inst_sve_clz_pred :: inst_sve_clz_pred_z_p_z
|
|
emit_sve_clz_pred :: emit_sve_clz_pred_z_p_z
|
|
inst_sve_cnt_pred :: inst_sve_cnt_pred_z_p_z
|
|
emit_sve_cnt_pred :: emit_sve_cnt_pred_z_p_z
|
|
inst_sve_mov_pred :: inst_sve_mov_pred_z_p_z
|
|
emit_sve_mov_pred :: emit_sve_mov_pred_z_p_z
|
|
inst_sve_fadd_z :: inst_sve_fadd_z_z_z_z
|
|
emit_sve_fadd_z :: emit_sve_fadd_z_z_z_z
|
|
inst_sve_fsub_z :: inst_sve_fsub_z_z_z_z
|
|
emit_sve_fsub_z :: emit_sve_fsub_z_z_z_z
|
|
inst_sve_fmul_z :: inst_sve_fmul_z_z_z_z
|
|
emit_sve_fmul_z :: emit_sve_fmul_z_z_z_z
|
|
inst_sve_frecps :: inst_sve_frecps_z_z_z
|
|
emit_sve_frecps :: emit_sve_frecps_z_z_z
|
|
inst_sve_frsqrts :: inst_sve_frsqrts_z_z_z
|
|
emit_sve_frsqrts :: emit_sve_frsqrts_z_z_z
|
|
inst_sve_ftsmul :: inst_sve_ftsmul_z_z_z
|
|
emit_sve_ftsmul :: emit_sve_ftsmul_z_z_z
|
|
inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z
|
|
emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z
|
|
inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z
|
|
emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z
|
|
inst_sve_fsubr_pred :: inst_sve_fsubr_pred_z_p_z_z
|
|
emit_sve_fsubr_pred :: emit_sve_fsubr_pred_z_p_z_z
|
|
inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z
|
|
emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z
|
|
inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z
|
|
emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z
|
|
inst_sve_fdivr_pred :: inst_sve_fdivr_pred_z_p_z_z
|
|
emit_sve_fdivr_pred :: emit_sve_fdivr_pred_z_p_z_z
|
|
inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z
|
|
emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z
|
|
inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z
|
|
emit_sve_fmin_pred :: emit_sve_fmin_pred_z_p_z_z
|
|
inst_sve_fmaxnm_pred :: inst_sve_fmaxnm_pred_z_p_z_z
|
|
emit_sve_fmaxnm_pred :: emit_sve_fmaxnm_pred_z_p_z_z
|
|
inst_sve_fminnm_pred :: inst_sve_fminnm_pred_z_p_z_z
|
|
emit_sve_fminnm_pred :: emit_sve_fminnm_pred_z_p_z_z
|
|
inst_sve_fabs_z :: inst_sve_fabs_z_z_p_z
|
|
emit_sve_fabs_z :: emit_sve_fabs_z_z_p_z
|
|
inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z
|
|
emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z
|
|
inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z
|
|
emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z
|
|
inst_sve_frecpx_z :: inst_sve_frecpx_z_z_p_z
|
|
emit_sve_frecpx_z :: emit_sve_frecpx_z_z_p_z
|
|
inst_sve_frintn :: inst_sve_frintn_z_p_z
|
|
emit_sve_frintn :: emit_sve_frintn_z_p_z
|
|
inst_sve_frintp :: inst_sve_frintp_z_p_z
|
|
emit_sve_frintp :: emit_sve_frintp_z_p_z
|
|
inst_sve_frintm :: inst_sve_frintm_z_p_z
|
|
emit_sve_frintm :: emit_sve_frintm_z_p_z
|
|
inst_sve_frintz :: inst_sve_frintz_z_p_z
|
|
emit_sve_frintz :: emit_sve_frintz_z_p_z
|
|
inst_sve_frinta :: inst_sve_frinta_z_p_z
|
|
emit_sve_frinta :: emit_sve_frinta_z_p_z
|
|
inst_sve_frintx :: inst_sve_frintx_z_p_z
|
|
emit_sve_frintx :: emit_sve_frintx_z_p_z
|
|
inst_sve_frinti :: inst_sve_frinti_z_p_z
|
|
emit_sve_frinti :: emit_sve_frinti_z_p_z
|
|
inst_sve_fmla :: inst_sve_fmla_z_p_z_z
|
|
emit_sve_fmla :: emit_sve_fmla_z_p_z_z
|
|
inst_sve_fmls :: inst_sve_fmls_z_p_z_z
|
|
emit_sve_fmls :: emit_sve_fmls_z_p_z_z
|
|
inst_sve_fnmla :: inst_sve_fnmla_z_p_z_z
|
|
emit_sve_fnmla :: emit_sve_fnmla_z_p_z_z
|
|
inst_sve_fnmls :: inst_sve_fnmls_z_p_z_z
|
|
emit_sve_fnmls :: emit_sve_fnmls_z_p_z_z
|
|
inst_sve_and_p :: inst_sve_and_p_p_p_p_p
|
|
emit_sve_and_p :: emit_sve_and_p_p_p_p_p
|
|
inst_sve_bic_p :: inst_sve_bic_p_p_p_p_p
|
|
emit_sve_bic_p :: emit_sve_bic_p_p_p_p_p
|
|
inst_sve_orr_p :: inst_sve_orr_p_p_p_p_p
|
|
emit_sve_orr_p :: emit_sve_orr_p_p_p_p_p
|
|
inst_sve_eor_p :: inst_sve_eor_p_p_p_p_p
|
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emit_sve_eor_p :: emit_sve_eor_p_p_p_p_p
|
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inst_sve_nand_p :: inst_sve_nand_p_p_p_p_p
|
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emit_sve_nand_p :: emit_sve_nand_p_p_p_p_p
|
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inst_sve_nor_p :: inst_sve_nor_p_p_p_p_p
|
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emit_sve_nor_p :: emit_sve_nor_p_p_p_p_p
|
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inst_sve_orn_p :: inst_sve_orn_p_p_p_p_p
|
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emit_sve_orn_p :: emit_sve_orn_p_p_p_p_p
|
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inst_sve_sel_p :: inst_sve_sel_p_p_p_p_p
|
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emit_sve_sel_p :: emit_sve_sel_p_p_p_p_p
|
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inst_sve_ands_p :: inst_sve_ands_p_p_p_p_p
|
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emit_sve_ands_p :: emit_sve_ands_p_p_p_p_p
|
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inst_sve_bics_p :: inst_sve_bics_p_p_p_p_p
|
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emit_sve_bics_p :: emit_sve_bics_p_p_p_p_p
|
|
inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p
|
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emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p
|
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inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p
|
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emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p
|
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inst_sve_nands_p :: inst_sve_nands_p_p_p_p_p
|
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emit_sve_nands_p :: emit_sve_nands_p_p_p_p_p
|
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inst_sve_nors_p :: inst_sve_nors_p_p_p_p_p
|
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emit_sve_nors_p :: emit_sve_nors_p_p_p_p_p
|
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inst_sve_orns_p :: inst_sve_orns_p_p_p_p_p
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emit_sve_orns_p :: emit_sve_orns_p_p_p_p_p
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inst_sve_not_p :: inst_sve_not_p_p_p_p
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emit_sve_not_p :: emit_sve_not_p_p_p_p
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inst_sve_mov_p :: proc{ inst_sve_mov_p_p_p_p, inst_sve_mov_p_p_p }
|
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emit_sve_mov_p :: proc{ emit_sve_mov_p_p_p_p, emit_sve_mov_p_p_p }
|
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inst_sve_movs_p :: inst_sve_movs_p_p_p_p
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emit_sve_movs_p :: emit_sve_movs_p_p_p_p
|
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inst_sve_ptrue :: inst_sve_ptrue_p_i
|
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emit_sve_ptrue :: emit_sve_ptrue_p_i
|
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inst_sve_ptrues :: inst_sve_ptrues_p_i
|
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emit_sve_ptrues :: emit_sve_ptrues_p_i
|
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inst_sve_pfalse :: inst_sve_pfalse_p
|
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emit_sve_pfalse :: emit_sve_pfalse_p
|
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inst_sve_pfirst :: inst_sve_pfirst_p_p_p
|
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emit_sve_pfirst :: emit_sve_pfirst_p_p_p
|
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inst_sve_pnext :: inst_sve_pnext_p_p_p
|
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emit_sve_pnext :: emit_sve_pnext_p_p_p
|
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inst_sve_brka :: inst_sve_brka_p_p_p
|
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emit_sve_brka :: emit_sve_brka_p_p_p
|
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inst_sve_brkb :: inst_sve_brkb_p_p_p
|
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emit_sve_brkb :: emit_sve_brkb_p_p_p
|
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inst_sve_brkas :: inst_sve_brkas_p_p_p
|
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emit_sve_brkas :: emit_sve_brkas_p_p_p
|
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inst_sve_brkbs :: inst_sve_brkbs_p_p_p
|
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emit_sve_brkbs :: emit_sve_brkbs_p_p_p
|
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inst_sve_brkpa :: inst_sve_brkpa_p_p_p_p
|
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emit_sve_brkpa :: emit_sve_brkpa_p_p_p_p
|
|
inst_sve_brkpb :: inst_sve_brkpb_p_p_p_p
|
|
emit_sve_brkpb :: emit_sve_brkpb_p_p_p_p
|
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inst_sve_brkn :: inst_sve_brkn_p_p_p_p
|
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emit_sve_brkn :: emit_sve_brkn_p_p_p_p
|
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inst_sve_rdffr :: inst_sve_rdffr_p
|
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emit_sve_rdffr :: emit_sve_rdffr_p
|
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inst_sve_wrffr :: inst_sve_wrffr_p
|
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emit_sve_wrffr :: emit_sve_wrffr_p
|
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inst_sve_setffr :: inst_sve_setffr_none
|
|
emit_sve_setffr :: emit_sve_setffr_none
|
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inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z
|
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emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z
|
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inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z
|
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emit_sve_cmpne :: emit_sve_cmpne_p_p_z_z
|
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inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z
|
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emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z
|
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inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z
|
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emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z
|
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inst_sve_cmple :: inst_sve_cmple_p_p_z_z
|
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emit_sve_cmple :: emit_sve_cmple_p_p_z_z
|
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inst_sve_cmplt :: inst_sve_cmplt_p_p_z_z
|
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emit_sve_cmplt :: emit_sve_cmplt_p_p_z_z
|
|
inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z
|
|
emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z
|
|
inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z
|
|
emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z
|
|
inst_sve_cmplo :: inst_sve_cmplo_p_p_z_z
|
|
emit_sve_cmplo :: emit_sve_cmplo_p_p_z_z
|
|
inst_sve_cmpls :: inst_sve_cmpls_p_p_z_z
|
|
emit_sve_cmpls :: emit_sve_cmpls_p_p_z_z
|
|
inst_sve_fcmeq :: inst_sve_fcmeq_p_p_z_z
|
|
emit_sve_fcmeq :: emit_sve_fcmeq_p_p_z_z
|
|
inst_sve_fcmne :: inst_sve_fcmne_p_p_z_z
|
|
emit_sve_fcmne :: emit_sve_fcmne_p_p_z_z
|
|
inst_sve_fcmge :: inst_sve_fcmge_p_p_z_z
|
|
emit_sve_fcmge :: emit_sve_fcmge_p_p_z_z
|
|
inst_sve_fcmgt :: inst_sve_fcmgt_p_p_z_z
|
|
emit_sve_fcmgt :: emit_sve_fcmgt_p_p_z_z
|
|
inst_sve_fcmle :: inst_sve_fcmle_p_p_z
|
|
emit_sve_fcmle :: emit_sve_fcmle_p_p_z
|
|
inst_sve_fcmlt :: inst_sve_fcmlt_p_p_z
|
|
emit_sve_fcmlt :: emit_sve_fcmlt_p_p_z
|
|
inst_sve_fcmuo :: inst_sve_fcmuo_p_p_z_z
|
|
emit_sve_fcmuo :: emit_sve_fcmuo_p_p_z_z
|
|
inst_sve_dup_z :: inst_sve_dup_z_z_r
|
|
emit_sve_dup_z :: emit_sve_dup_z_z_r
|
|
inst_sve_insr :: inst_sve_insr_z_r
|
|
emit_sve_insr :: emit_sve_insr_z_r
|
|
inst_sve_rev_z :: inst_sve_rev_z_z_z
|
|
emit_sve_rev_z :: emit_sve_rev_z_z_z
|
|
inst_sve_rev_p :: inst_sve_rev_p_p_p
|
|
emit_sve_rev_p :: emit_sve_rev_p_p_p
|
|
inst_sve_tbl :: inst_sve_tbl_z_z_z
|
|
emit_sve_tbl :: emit_sve_tbl_z_z_z
|
|
inst_sve_zip1_z :: inst_sve_zip1_z_z_z_z
|
|
emit_sve_zip1_z :: emit_sve_zip1_z_z_z_z
|
|
inst_sve_zip2_z :: inst_sve_zip2_z_z_z_z
|
|
emit_sve_zip2_z :: emit_sve_zip2_z_z_z_z
|
|
inst_sve_uzp1_z :: inst_sve_uzp1_z_z_z_z
|
|
emit_sve_uzp1_z :: emit_sve_uzp1_z_z_z_z
|
|
inst_sve_uzp2_z :: inst_sve_uzp2_z_z_z_z
|
|
emit_sve_uzp2_z :: emit_sve_uzp2_z_z_z_z
|
|
inst_sve_trn1_z :: inst_sve_trn1_z_z_z_z
|
|
emit_sve_trn1_z :: emit_sve_trn1_z_z_z_z
|
|
inst_sve_trn2_z :: inst_sve_trn2_z_z_z_z
|
|
emit_sve_trn2_z :: emit_sve_trn2_z_z_z_z
|
|
inst_sve_zip1_p :: inst_sve_zip1_p_p_p_p
|
|
emit_sve_zip1_p :: emit_sve_zip1_p_p_p_p
|
|
inst_sve_zip2_p :: inst_sve_zip2_p_p_p_p
|
|
emit_sve_zip2_p :: emit_sve_zip2_p_p_p_p
|
|
inst_sve_uzp1_p :: inst_sve_uzp1_p_p_p_p
|
|
emit_sve_uzp1_p :: emit_sve_uzp1_p_p_p_p
|
|
inst_sve_uzp2_p :: inst_sve_uzp2_p_p_p_p
|
|
emit_sve_uzp2_p :: emit_sve_uzp2_p_p_p_p
|
|
inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p
|
|
emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p
|
|
inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p
|
|
emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p
|
|
inst_sve_cpy_z :: inst_sve_cpy_z_z_p_r
|
|
emit_sve_cpy_z :: emit_sve_cpy_z_z_p_r
|
|
inst_sve_compact :: inst_sve_compact_z_p_z
|
|
emit_sve_compact :: emit_sve_compact_z_p_z
|
|
inst_sve_ext_z :: inst_sve_ext_z_z_z_z_i
|
|
emit_sve_ext_z :: emit_sve_ext_z_z_z_z_i
|
|
inst_sve_ld1b :: inst_sve_ld1b_z_p_m
|
|
emit_sve_ld1b :: emit_sve_ld1b_z_p_m
|
|
inst_sve_ld1h :: inst_sve_ld1h_z_p_m
|
|
emit_sve_ld1h :: emit_sve_ld1h_z_p_m
|
|
inst_sve_ld1w :: inst_sve_ld1w_z_p_m
|
|
emit_sve_ld1w :: emit_sve_ld1w_z_p_m
|
|
inst_sve_ld1d :: inst_sve_ld1d_z_p_m
|
|
emit_sve_ld1d :: emit_sve_ld1d_z_p_m
|
|
inst_sve_ld1sb :: inst_sve_ld1sb_z_p_m
|
|
emit_sve_ld1sb :: emit_sve_ld1sb_z_p_m
|
|
inst_sve_ld1sh :: inst_sve_ld1sh_z_p_m
|
|
emit_sve_ld1sh :: emit_sve_ld1sh_z_p_m
|
|
inst_sve_ld1sw :: inst_sve_ld1sw_z_p_m
|
|
emit_sve_ld1sw :: emit_sve_ld1sw_z_p_m
|
|
inst_sve_st1b :: inst_sve_st1b_z_p_m
|
|
emit_sve_st1b :: emit_sve_st1b_z_p_m
|
|
inst_sve_st1h :: inst_sve_st1h_z_p_m
|
|
emit_sve_st1h :: emit_sve_st1h_z_p_m
|
|
inst_sve_st1w :: inst_sve_st1w_z_p_m
|
|
emit_sve_st1w :: emit_sve_st1w_z_p_m
|
|
inst_sve_st1d :: inst_sve_st1d_z_p_m
|
|
emit_sve_st1d :: emit_sve_st1d_z_p_m
|
|
inst_sve_ldr_z :: inst_sve_ldr_z_z_m
|
|
emit_sve_ldr_z :: emit_sve_ldr_z_z_m
|
|
inst_sve_str_z :: inst_sve_str_z_z_m
|
|
emit_sve_str_z :: emit_sve_str_z_z_m
|
|
inst_sve_ldr_p :: inst_sve_ldr_p_p_m
|
|
emit_sve_ldr_p :: emit_sve_ldr_p_p_m
|
|
inst_sve_str_p :: inst_sve_str_p_p_m
|
|
emit_sve_str_p :: emit_sve_str_p_p_m
|
|
inst_sve_ldff1b :: inst_sve_ldff1b_z_p_m
|
|
emit_sve_ldff1b :: emit_sve_ldff1b_z_p_m
|
|
inst_sve_ldff1h :: inst_sve_ldff1h_z_p_m
|
|
emit_sve_ldff1h :: emit_sve_ldff1h_z_p_m
|
|
inst_sve_ldff1w :: inst_sve_ldff1w_z_p_m
|
|
emit_sve_ldff1w :: emit_sve_ldff1w_z_p_m
|
|
inst_sve_ldff1d :: inst_sve_ldff1d_z_p_m
|
|
emit_sve_ldff1d :: emit_sve_ldff1d_z_p_m
|
|
inst_sve_whilege :: inst_sve_whilege_p_r_r
|
|
emit_sve_whilege :: emit_sve_whilege_p_r_r
|
|
inst_sve_whilegt :: inst_sve_whilegt_p_r_r
|
|
emit_sve_whilegt :: emit_sve_whilegt_p_r_r
|
|
inst_sve_whilele :: inst_sve_whilele_p_r_r
|
|
emit_sve_whilele :: emit_sve_whilele_p_r_r
|
|
inst_sve_whilelt :: inst_sve_whilelt_p_r_r
|
|
emit_sve_whilelt :: emit_sve_whilelt_p_r_r
|
|
inst_sve_whilehi :: inst_sve_whilehi_p_r_r
|
|
emit_sve_whilehi :: emit_sve_whilehi_p_r_r
|
|
inst_sve_whilehs :: inst_sve_whilehs_p_r_r
|
|
emit_sve_whilehs :: emit_sve_whilehs_p_r_r
|
|
inst_sve_whilelo :: inst_sve_whilelo_p_r_r
|
|
emit_sve_whilelo :: emit_sve_whilelo_p_r_r
|
|
inst_sve_whilels :: inst_sve_whilels_p_r_r
|
|
emit_sve_whilels :: emit_sve_whilels_p_r_r
|
|
inst_sve_sqrdmlah :: inst_sve_sqrdmlah_z_z_z
|
|
emit_sve_sqrdmlah :: emit_sve_sqrdmlah_z_z_z
|
|
inst_sve_sqrdmlsh :: inst_sve_sqrdmlsh_z_z_z
|
|
emit_sve_sqrdmlsh :: emit_sve_sqrdmlsh_z_z_z
|
|
inst_sve_adclb :: inst_sve_adclb_z_z_z
|
|
emit_sve_adclb :: emit_sve_adclb_z_z_z
|
|
inst_sve_adclt :: inst_sve_adclt_z_z_z
|
|
emit_sve_adclt :: emit_sve_adclt_z_z_z
|
|
inst_sve_sbclb :: inst_sve_sbclb_z_z_z
|
|
emit_sve_sbclb :: emit_sve_sbclb_z_z_z
|
|
inst_sve_sbclt :: inst_sve_sbclt_z_z_z
|
|
emit_sve_sbclt :: emit_sve_sbclt_z_z_z
|
|
inst_sve_tbl2 :: inst_sve_tbl2_z_z_z
|
|
emit_sve_tbl2 :: emit_sve_tbl2_z_z_z
|
|
inst_sve_tbx :: inst_sve_tbx_z_z_z
|
|
emit_sve_tbx :: emit_sve_tbx_z_z_z
|
|
inst_sve_aese :: inst_sve_aese_z_z
|
|
emit_sve_aese :: emit_sve_aese_z_z
|
|
inst_sve_aesd :: inst_sve_aesd_z_z
|
|
emit_sve_aesd :: emit_sve_aesd_z_z
|
|
inst_sve_aesmc :: inst_sve_aesmc_z
|
|
emit_sve_aesmc :: emit_sve_aesmc_z
|
|
inst_sve_aesimc :: inst_sve_aesimc_z
|
|
emit_sve_aesimc :: emit_sve_aesimc_z
|
|
inst_sve_bcax_z :: inst_sve_bcax_z_z_z_z_z
|
|
emit_sve_bcax_z :: emit_sve_bcax_z_z_z_z_z
|
|
inst_sve_xar_z :: inst_sve_xar_z_z_z_z_i
|
|
emit_sve_xar_z :: emit_sve_xar_z_z_z_z_i
|
|
inst_sve_eor3_z :: inst_sve_eor3_z_z_z_z_z
|
|
emit_sve_eor3_z :: emit_sve_eor3_z_z_z_z_z
|
|
inst_sve_match :: inst_sve_match_p_p_z_z
|
|
emit_sve_match :: emit_sve_match_p_p_z_z
|
|
inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z
|
|
emit_sve_nmatch :: emit_sve_nmatch_p_p_z_z
|
|
inst_sve_histcnt :: inst_sve_histcnt_z_p_z_z
|
|
emit_sve_histcnt :: emit_sve_histcnt_z_p_z_z
|
|
inst_sve_histseg :: inst_sve_histseg_z_z_z
|
|
emit_sve_histseg :: emit_sve_histseg_z_z_z
|
|
inst_sme_smstart :: inst_sme_smstart_none
|
|
emit_sme_smstart :: emit_sme_smstart_none
|
|
inst_sme_smstop :: inst_sme_smstop_none
|
|
emit_sme_smstop :: emit_sme_smstop_none
|
|
inst_sme_rdsvl :: inst_sme_rdsvl_r_i
|
|
emit_sme_rdsvl :: emit_sme_rdsvl_r_i
|
|
inst_sme_addha :: inst_sme_addha_i_p_p_z
|
|
emit_sme_addha :: emit_sme_addha_i_p_p_z
|
|
inst_sme_addva :: inst_sme_addva_i_p_p_z
|
|
emit_sme_addva :: emit_sme_addva_i_p_p_z
|
|
inst_sme_zero :: inst_sme_zero_i
|
|
emit_sme_zero :: emit_sme_zero_i
|
|
inst_sme_fmopa :: inst_sme_fmopa_i_p_p_z
|
|
emit_sme_fmopa :: emit_sme_fmopa_i_p_p_z
|
|
inst_sme_fmops :: inst_sme_fmops_i_p_p_z
|
|
emit_sme_fmops :: emit_sme_fmops_i_p_p_z
|
|
inst_sme_bfmopa :: inst_sme_bfmopa_i_p_p_z
|
|
emit_sme_bfmopa :: emit_sme_bfmopa_i_p_p_z
|
|
inst_sme_bfmops :: inst_sme_bfmops_i_p_p_z
|
|
emit_sme_bfmops :: emit_sme_bfmops_i_p_p_z
|
|
inst_sme_smopa :: inst_sme_smopa_i_p_p_z
|
|
emit_sme_smopa :: emit_sme_smopa_i_p_p_z
|
|
inst_sme_smops :: inst_sme_smops_i_p_p_z
|
|
emit_sme_smops :: emit_sme_smops_i_p_p_z
|
|
inst_sme_umopa :: inst_sme_umopa_i_p_p_z
|
|
emit_sme_umopa :: emit_sme_umopa_i_p_p_z
|
|
inst_sme_umops :: inst_sme_umops_i_p_p_z
|
|
emit_sme_umops :: emit_sme_umops_i_p_p_z
|
|
inst_sme_usmopa :: inst_sme_usmopa_i_p_p_z
|
|
emit_sme_usmopa :: emit_sme_usmopa_i_p_p_z
|
|
inst_sme_sumopa :: inst_sme_sumopa_i_p_p_z
|
|
emit_sme_sumopa :: emit_sme_sumopa_i_p_p_z
|
|
inst_sme_ldr_za :: inst_sme_ldr_za_i_m
|
|
emit_sme_ldr_za :: emit_sme_ldr_za_i_m
|
|
inst_sme_str_za :: inst_sme_str_za_i_m
|
|
emit_sme_str_za :: emit_sme_str_za_i_m
|
|
inst_sve_fmla_idx_h :: inst_sve_fmla_idx_h_z_z_z_i
|
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emit_sve_fmla_idx_h :: emit_sve_fmla_idx_h_z_z_z_i
|
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inst_sve_fmla_idx_s :: inst_sve_fmla_idx_s_z_z_z_i
|
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emit_sve_fmla_idx_s :: emit_sve_fmla_idx_s_z_z_z_i
|
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inst_sve_fmla_idx_d :: inst_sve_fmla_idx_d_z_z_z_i
|
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emit_sve_fmla_idx_d :: emit_sve_fmla_idx_d_z_z_z_i
|
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inst_sve_fmls_idx_h :: inst_sve_fmls_idx_h_z_z_z_i
|
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emit_sve_fmls_idx_h :: emit_sve_fmls_idx_h_z_z_z_i
|
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inst_sve_fmls_idx_s :: inst_sve_fmls_idx_s_z_z_z_i
|
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emit_sve_fmls_idx_s :: emit_sve_fmls_idx_s_z_z_z_i
|
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inst_sve_fmls_idx_d :: inst_sve_fmls_idx_d_z_z_z_i
|
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emit_sve_fmls_idx_d :: emit_sve_fmls_idx_d_z_z_z_i
|
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inst_sve_ld1b_gather_s :: inst_sve_ld1b_gather_s_z_p_m
|
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emit_sve_ld1b_gather_s :: emit_sve_ld1b_gather_s_z_p_m
|
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inst_sve_ld1b_gather_d :: inst_sve_ld1b_gather_d_z_p_m
|
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emit_sve_ld1b_gather_d :: emit_sve_ld1b_gather_d_z_p_m
|
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inst_sve_ld1h_gather_s :: inst_sve_ld1h_gather_s_z_p_m
|
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emit_sve_ld1h_gather_s :: emit_sve_ld1h_gather_s_z_p_m
|
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inst_sve_ld1h_gather_d :: inst_sve_ld1h_gather_d_z_p_m
|
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emit_sve_ld1h_gather_d :: emit_sve_ld1h_gather_d_z_p_m
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inst_sve_ld1w_gather_s :: inst_sve_ld1w_gather_s_z_p_m
|
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emit_sve_ld1w_gather_s :: emit_sve_ld1w_gather_s_z_p_m
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inst_sve_ld1w_gather_d :: inst_sve_ld1w_gather_d_z_p_m
|
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emit_sve_ld1w_gather_d :: emit_sve_ld1w_gather_d_z_p_m
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inst_sve_ld1d_gather_d :: inst_sve_ld1d_gather_d_z_p_m
|
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emit_sve_ld1d_gather_d :: emit_sve_ld1d_gather_d_z_p_m
|
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inst_sve_ld1sb_gather_s :: inst_sve_ld1sb_gather_s_z_p_m
|
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emit_sve_ld1sb_gather_s :: emit_sve_ld1sb_gather_s_z_p_m
|
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inst_sve_ld1sb_gather_d :: inst_sve_ld1sb_gather_d_z_p_m
|
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emit_sve_ld1sb_gather_d :: emit_sve_ld1sb_gather_d_z_p_m
|
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inst_sve_ld1sh_gather_s :: inst_sve_ld1sh_gather_s_z_p_m
|
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emit_sve_ld1sh_gather_s :: emit_sve_ld1sh_gather_s_z_p_m
|
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inst_sve_ld1sh_gather_d :: inst_sve_ld1sh_gather_d_z_p_m
|
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emit_sve_ld1sh_gather_d :: emit_sve_ld1sh_gather_d_z_p_m
|
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inst_sve_ld1sw_gather_d :: inst_sve_ld1sw_gather_d_z_p_m
|
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emit_sve_ld1sw_gather_d :: emit_sve_ld1sw_gather_d_z_p_m
|
|
inst_sve_st1b_scatter_s :: inst_sve_st1b_scatter_s_z_p_m
|
|
emit_sve_st1b_scatter_s :: emit_sve_st1b_scatter_s_z_p_m
|
|
inst_sve_st1b_scatter_d :: inst_sve_st1b_scatter_d_z_p_m
|
|
emit_sve_st1b_scatter_d :: emit_sve_st1b_scatter_d_z_p_m
|
|
inst_sve_st1h_scatter_s :: inst_sve_st1h_scatter_s_z_p_m
|
|
emit_sve_st1h_scatter_s :: emit_sve_st1h_scatter_s_z_p_m
|
|
inst_sve_st1h_scatter_d :: inst_sve_st1h_scatter_d_z_p_m
|
|
emit_sve_st1h_scatter_d :: emit_sve_st1h_scatter_d_z_p_m
|
|
inst_sve_st1w_scatter_s :: inst_sve_st1w_scatter_s_z_p_m
|
|
emit_sve_st1w_scatter_s :: emit_sve_st1w_scatter_s_z_p_m
|
|
inst_sve_st1w_scatter_d :: inst_sve_st1w_scatter_d_z_p_m
|
|
emit_sve_st1w_scatter_d :: emit_sve_st1w_scatter_d_z_p_m
|
|
inst_sve_st1d_scatter_d :: inst_sve_st1d_scatter_d_z_p_m
|
|
emit_sve_st1d_scatter_d :: emit_sve_st1d_scatter_d_z_p_m
|
|
inst_sme_ld1b_tile :: inst_sme_ld1b_tile_i_p_m
|
|
emit_sme_ld1b_tile :: emit_sme_ld1b_tile_i_p_m
|
|
inst_sme_ld1h_tile :: inst_sme_ld1h_tile_i_p_m
|
|
emit_sme_ld1h_tile :: emit_sme_ld1h_tile_i_p_m
|
|
inst_sme_ld1w_tile :: inst_sme_ld1w_tile_i_p_m
|
|
emit_sme_ld1w_tile :: emit_sme_ld1w_tile_i_p_m
|
|
inst_sme_ld1d_tile :: inst_sme_ld1d_tile_i_p_m
|
|
emit_sme_ld1d_tile :: emit_sme_ld1d_tile_i_p_m
|
|
inst_sme_ld1q_tile :: inst_sme_ld1q_tile_i_p_m
|
|
emit_sme_ld1q_tile :: emit_sme_ld1q_tile_i_p_m
|
|
inst_sme_st1b_tile :: inst_sme_st1b_tile_i_p_m
|
|
emit_sme_st1b_tile :: emit_sme_st1b_tile_i_p_m
|
|
inst_sme_st1h_tile :: inst_sme_st1h_tile_i_p_m
|
|
emit_sme_st1h_tile :: emit_sme_st1h_tile_i_p_m
|
|
inst_sme_st1w_tile :: inst_sme_st1w_tile_i_p_m
|
|
emit_sme_st1w_tile :: emit_sme_st1w_tile_i_p_m
|
|
inst_sme_st1d_tile :: inst_sme_st1d_tile_i_p_m
|
|
emit_sme_st1d_tile :: emit_sme_st1d_tile_i_p_m
|
|
inst_sme_st1q_tile :: inst_sme_st1q_tile_i_p_m
|
|
emit_sme_st1q_tile :: emit_sme_st1q_tile_i_p_m
|
|
inst_sme_mova_z_from_tile :: inst_sme_mova_z_from_tile_z_p_i
|
|
emit_sme_mova_z_from_tile :: emit_sme_mova_z_from_tile_z_p_i
|
|
inst_sme_mova_tile_from_z :: inst_sme_mova_tile_from_z_i_p_z
|
|
emit_sme_mova_tile_from_z :: emit_sme_mova_tile_from_z_i_p_z
|
|
inst_fcmla_4h :: inst_fcmla_4h_r_r_r_i
|
|
emit_fcmla_4h :: emit_fcmla_4h_r_r_r_i
|
|
inst_fcmla_8h :: inst_fcmla_8h_r_r_r_i
|
|
emit_fcmla_8h :: emit_fcmla_8h_r_r_r_i
|
|
inst_fcmla_4s :: inst_fcmla_4s_r_r_r_i
|
|
emit_fcmla_4s :: emit_fcmla_4s_r_r_r_i
|
|
inst_fcmla_2d :: inst_fcmla_2d_r_r_r_i
|
|
emit_fcmla_2d :: emit_fcmla_2d_r_r_r_i
|
|
inst_fcadd_4h :: inst_fcadd_4h_r_r_r_i
|
|
emit_fcadd_4h :: emit_fcadd_4h_r_r_r_i
|
|
inst_fcadd_8h :: inst_fcadd_8h_r_r_r_i
|
|
emit_fcadd_8h :: emit_fcadd_8h_r_r_r_i
|
|
inst_fcadd_4s :: inst_fcadd_4s_r_r_r_i
|
|
emit_fcadd_4s :: emit_fcadd_4s_r_r_r_i
|
|
inst_fcadd_2d :: inst_fcadd_2d_r_r_r_i
|
|
emit_fcadd_2d :: emit_fcadd_2d_r_r_r_i
|
|
inst_sve_prfb :: inst_sve_prfb_i_p_m
|
|
emit_sve_prfb :: emit_sve_prfb_i_p_m
|
|
inst_sve_prfh :: inst_sve_prfh_i_p_m
|
|
emit_sve_prfh :: emit_sve_prfh_i_p_m
|
|
inst_sve_prfw :: inst_sve_prfw_i_p_m
|
|
emit_sve_prfw :: emit_sve_prfw_i_p_m
|
|
inst_sve_prfd :: inst_sve_prfd_i_p_m
|
|
emit_sve_prfd :: emit_sve_prfd_i_p_m
|
|
inst_sve_ldnt1b :: inst_sve_ldnt1b_z_p_m
|
|
emit_sve_ldnt1b :: emit_sve_ldnt1b_z_p_m
|
|
inst_sve_ldnt1h :: inst_sve_ldnt1h_z_p_m
|
|
emit_sve_ldnt1h :: emit_sve_ldnt1h_z_p_m
|
|
inst_sve_ldnt1w :: inst_sve_ldnt1w_z_p_m
|
|
emit_sve_ldnt1w :: emit_sve_ldnt1w_z_p_m
|
|
inst_sve_ldnt1d :: inst_sve_ldnt1d_z_p_m
|
|
emit_sve_ldnt1d :: emit_sve_ldnt1d_z_p_m
|
|
inst_sve_stnt1b :: inst_sve_stnt1b_z_p_m
|
|
emit_sve_stnt1b :: emit_sve_stnt1b_z_p_m
|
|
inst_sve_stnt1h :: inst_sve_stnt1h_z_p_m
|
|
emit_sve_stnt1h :: emit_sve_stnt1h_z_p_m
|
|
inst_sve_stnt1w :: inst_sve_stnt1w_z_p_m
|
|
emit_sve_stnt1w :: emit_sve_stnt1w_z_p_m
|
|
inst_sve_stnt1d :: inst_sve_stnt1d_z_p_m
|
|
emit_sve_stnt1d :: emit_sve_stnt1d_z_p_m
|
|
inst_sve_ext :: inst_sve_ext_z_z_z_i
|
|
emit_sve_ext :: emit_sve_ext_z_z_z_i
|
|
inst_sve_splice :: inst_sve_splice_z_p_z_z
|
|
emit_sve_splice :: emit_sve_splice_z_p_z_z
|
|
inst_sve_index_ii :: inst_sve_index_ii_z_i_i
|
|
emit_sve_index_ii :: emit_sve_index_ii_z_i_i
|
|
inst_sve_index_ir :: inst_sve_index_ir_z_i_r
|
|
emit_sve_index_ir :: emit_sve_index_ir_z_i_r
|
|
inst_sve_index_ri :: inst_sve_index_ri_z_r_i
|
|
emit_sve_index_ri :: emit_sve_index_ri_z_r_i
|
|
inst_sve_index_rr :: inst_sve_index_rr_z_r_r
|
|
emit_sve_index_rr :: emit_sve_index_rr_z_r_r
|
|
inst_sve_bsl :: inst_sve_bsl_z_z_z_z
|
|
emit_sve_bsl :: emit_sve_bsl_z_z_z_z
|
|
inst_sve_bsl1n :: inst_sve_bsl1n_z_z_z_z
|
|
emit_sve_bsl1n :: emit_sve_bsl1n_z_z_z_z
|
|
inst_sve_bsl2n :: inst_sve_bsl2n_z_z_z_z
|
|
emit_sve_bsl2n :: emit_sve_bsl2n_z_z_z_z
|
|
inst_sve_nbsl :: inst_sve_nbsl_z_z_z_z
|
|
emit_sve_nbsl :: emit_sve_nbsl_z_z_z_z
|
|
inst_sve_pmul_vec :: inst_sve_pmul_vec_z_z_z
|
|
emit_sve_pmul_vec :: emit_sve_pmul_vec_z_z_z
|
|
inst_sve_pmullb :: inst_sve_pmullb_z_z_z
|
|
emit_sve_pmullb :: emit_sve_pmullb_z_z_z
|
|
inst_sve_pmullt :: inst_sve_pmullt_z_z_z
|
|
emit_sve_pmullt :: emit_sve_pmullt_z_z_z
|
|
inst_sve_bfcvt :: inst_sve_bfcvt_z_p_z
|
|
emit_sve_bfcvt :: emit_sve_bfcvt_z_p_z
|
|
inst_sve_bfcvtnt :: inst_sve_bfcvtnt_z_p_z
|
|
emit_sve_bfcvtnt :: emit_sve_bfcvtnt_z_p_z
|
|
inst_ldraa :: inst_ldraa_r_m
|
|
emit_ldraa :: emit_ldraa_r_m
|
|
inst_ldrab :: inst_ldrab_r_m
|
|
emit_ldrab :: emit_ldrab_r_m
|
|
inst_ldraa_pre :: inst_ldraa_pre_r_m
|
|
emit_ldraa_pre :: emit_ldraa_pre_r_m
|
|
inst_ldrab_pre :: inst_ldrab_pre_r_m
|
|
emit_ldrab_pre :: emit_ldrab_pre_r_m
|
|
inst_tstart :: inst_tstart_r
|
|
emit_tstart :: emit_tstart_r
|
|
inst_tcommit :: inst_tcommit_none
|
|
emit_tcommit :: emit_tcommit_none
|
|
inst_tcancel :: inst_tcancel_i
|
|
emit_tcancel :: emit_tcancel_i
|
|
inst_ttest :: inst_ttest_r
|
|
emit_ttest :: emit_ttest_r
|
|
inst_wfet :: inst_wfet_r
|
|
emit_wfet :: emit_wfet_r
|
|
inst_wfit :: inst_wfit_r
|
|
emit_wfit :: emit_wfit_r
|
|
inst_bc_cond :: inst_bc_cond_c_l
|
|
emit_bc_cond :: emit_bc_cond_c_l
|
|
inst_uxtb :: inst_uxtb_r_r
|
|
emit_uxtb :: emit_uxtb_r_r
|
|
inst_uxth :: inst_uxth_r_r
|
|
emit_uxth :: emit_uxth_r_r
|
|
inst_uxtw :: inst_uxtw_r_r
|
|
emit_uxtw :: emit_uxtw_r_r
|
|
inst_sxtb :: inst_sxtb_r_r
|
|
emit_sxtb :: emit_sxtb_r_r
|
|
inst_sxth :: inst_sxth_r_r
|
|
emit_sxth :: emit_sxth_r_r
|
|
inst_sxtw :: inst_sxtw_r_r
|
|
emit_sxtw :: emit_sxtw_r_r
|
|
inst_adc :: inst_adc_r_r_r
|
|
emit_adc :: emit_adc_r_r_r
|
|
inst_adcs :: inst_adcs_r_r_r
|
|
emit_adcs :: emit_adcs_r_r_r
|
|
inst_sbc :: inst_sbc_r_r_r
|
|
emit_sbc :: emit_sbc_r_r_r
|
|
inst_sbcs :: inst_sbcs_r_r_r
|
|
emit_sbcs :: emit_sbcs_r_r_r
|
|
inst_ngc :: inst_ngc_r_r
|
|
emit_ngc :: emit_ngc_r_r
|
|
inst_ngcs :: inst_ngcs_r_r
|
|
emit_ngcs :: emit_ngcs_r_r
|
|
inst_ldapur :: inst_ldapur_r_m
|
|
emit_ldapur :: emit_ldapur_r_m
|
|
inst_stlur :: inst_stlur_r_m
|
|
emit_stlur :: emit_stlur_r_m
|
|
inst_ldapurb :: inst_ldapurb_r_m
|
|
emit_ldapurb :: emit_ldapurb_r_m
|
|
inst_stlurb :: inst_stlurb_r_m
|
|
emit_stlurb :: emit_stlurb_r_m
|
|
inst_ldapurh :: inst_ldapurh_r_m
|
|
emit_ldapurh :: emit_ldapurh_r_m
|
|
inst_stlurh :: inst_stlurh_r_m
|
|
emit_stlurh :: emit_stlurh_r_m
|
|
inst_ldapursb :: inst_ldapursb_r_m
|
|
emit_ldapursb :: emit_ldapursb_r_m
|
|
inst_ldapursh :: inst_ldapursh_r_m
|
|
emit_ldapursh :: emit_ldapursh_r_m
|
|
inst_ldapursw :: inst_ldapursw_r_m
|
|
emit_ldapursw :: emit_ldapursw_r_m
|
|
inst_sve_bfadd :: inst_sve_bfadd_z_p_z_z
|
|
emit_sve_bfadd :: emit_sve_bfadd_z_p_z_z
|
|
inst_sve_bfsub :: inst_sve_bfsub_z_p_z_z
|
|
emit_sve_bfsub :: emit_sve_bfsub_z_p_z_z
|
|
inst_sve_bfmul :: inst_sve_bfmul_z_p_z_z
|
|
emit_sve_bfmul :: emit_sve_bfmul_z_p_z_z
|
|
inst_sve_bfmla :: inst_sve_bfmla_z_p_z_z
|
|
emit_sve_bfmla :: emit_sve_bfmla_z_p_z_z
|
|
inst_sve_bfmls :: inst_sve_bfmls_z_p_z_z
|
|
emit_sve_bfmls :: emit_sve_bfmls_z_p_z_z
|
|
inst_sb :: inst_sb_none
|
|
emit_sb :: emit_sb_none
|
|
inst_csdb :: inst_csdb_none
|
|
emit_csdb :: emit_csdb_none
|
|
inst_dgh :: inst_dgh_none
|
|
emit_dgh :: emit_dgh_none
|
|
inst_psb_csync :: inst_psb_csync_none
|
|
emit_psb_csync :: emit_psb_csync_none
|
|
inst_tsb_csync :: inst_tsb_csync_none
|
|
emit_tsb_csync :: emit_tsb_csync_none
|
|
inst_bti_j :: inst_bti_j_none
|
|
emit_bti_j :: emit_bti_j_none
|
|
inst_bti_c :: inst_bti_c_none
|
|
emit_bti_c :: emit_bti_c_none
|
|
inst_bti_jc :: inst_bti_jc_none
|
|
emit_bti_jc :: emit_bti_jc_none
|
|
inst_mov_v_alias :: inst_mov_v_alias_r_r
|
|
emit_mov_v_alias :: emit_mov_v_alias_r_r
|
|
inst_not_v_alias :: inst_not_v_alias_r_r
|
|
emit_not_v_alias :: emit_not_v_alias_r_r
|
|
inst_lsl_imm :: inst_lsl_imm_r_r_i
|
|
emit_lsl_imm :: emit_lsl_imm_r_r_i
|
|
inst_lsr_imm :: inst_lsr_imm_r_r_i
|
|
emit_lsr_imm :: emit_lsr_imm_r_r_i
|
|
inst_asr_imm :: inst_asr_imm_r_r_i
|
|
emit_asr_imm :: emit_asr_imm_r_r_i
|
|
inst_ror_imm :: inst_ror_imm_r_r_i
|
|
emit_ror_imm :: emit_ror_imm_r_r_i
|
|
inst_sve_bfadd_unpred :: inst_sve_bfadd_unpred_z_z_z
|
|
emit_sve_bfadd_unpred :: emit_sve_bfadd_unpred_z_z_z
|
|
inst_sve_bfsub_unpred :: inst_sve_bfsub_unpred_z_z_z
|
|
emit_sve_bfsub_unpred :: emit_sve_bfsub_unpred_z_z_z
|
|
inst_sve_bfmul_unpred :: inst_sve_bfmul_unpred_z_z_z
|
|
emit_sve_bfmul_unpred :: emit_sve_bfmul_unpred_z_z_z
|
|
inst_sve_bfclamp :: inst_sve_bfclamp_z_z_z
|
|
emit_sve_bfclamp :: emit_sve_bfclamp_z_z_z
|
|
inst_sve_bfmaxnm :: inst_sve_bfmaxnm_z_p_z_z
|
|
emit_sve_bfmaxnm :: emit_sve_bfmaxnm_z_p_z_z
|
|
inst_sve_bfminnm :: inst_sve_bfminnm_z_p_z_z
|
|
emit_sve_bfminnm :: emit_sve_bfminnm_z_p_z_z
|
|
inst_sme2_luti2_b :: inst_sme2_luti2_b_z_z_z_i
|
|
emit_sme2_luti2_b :: emit_sme2_luti2_b_z_z_z_i
|
|
inst_sme2_luti4_b :: inst_sme2_luti4_b_z_z_z_i
|
|
emit_sme2_luti4_b :: emit_sme2_luti4_b_z_z_z_i
|
|
inst_sme2_ld1b_x2 :: inst_sme2_ld1b_x2_z_p_m
|
|
emit_sme2_ld1b_x2 :: emit_sme2_ld1b_x2_z_p_m
|
|
inst_sme2_ld1h_x2 :: inst_sme2_ld1h_x2_z_p_m
|
|
emit_sme2_ld1h_x2 :: emit_sme2_ld1h_x2_z_p_m
|
|
inst_sme2_ld1w_x2 :: inst_sme2_ld1w_x2_z_p_m
|
|
emit_sme2_ld1w_x2 :: emit_sme2_ld1w_x2_z_p_m
|
|
inst_sme2_ld1d_x2 :: inst_sme2_ld1d_x2_z_p_m
|
|
emit_sme2_ld1d_x2 :: emit_sme2_ld1d_x2_z_p_m
|
|
inst_sme2_ld1b_x4 :: inst_sme2_ld1b_x4_z_p_m
|
|
emit_sme2_ld1b_x4 :: emit_sme2_ld1b_x4_z_p_m
|
|
inst_sme2_ld1h_x4 :: inst_sme2_ld1h_x4_z_p_m
|
|
emit_sme2_ld1h_x4 :: emit_sme2_ld1h_x4_z_p_m
|
|
inst_sme2_ld1w_x4 :: inst_sme2_ld1w_x4_z_p_m
|
|
emit_sme2_ld1w_x4 :: emit_sme2_ld1w_x4_z_p_m
|
|
inst_sme2_ld1d_x4 :: inst_sme2_ld1d_x4_z_p_m
|
|
emit_sme2_ld1d_x4 :: emit_sme2_ld1d_x4_z_p_m
|
|
inst_sme2_st1b_x2 :: inst_sme2_st1b_x2_z_p_m
|
|
emit_sme2_st1b_x2 :: emit_sme2_st1b_x2_z_p_m
|
|
inst_sme2_st1h_x2 :: inst_sme2_st1h_x2_z_p_m
|
|
emit_sme2_st1h_x2 :: emit_sme2_st1h_x2_z_p_m
|
|
inst_sme2_st1w_x2 :: inst_sme2_st1w_x2_z_p_m
|
|
emit_sme2_st1w_x2 :: emit_sme2_st1w_x2_z_p_m
|
|
inst_sme2_st1d_x2 :: inst_sme2_st1d_x2_z_p_m
|
|
emit_sme2_st1d_x2 :: emit_sme2_st1d_x2_z_p_m
|
|
inst_sme2_st1b_x4 :: inst_sme2_st1b_x4_z_p_m
|
|
emit_sme2_st1b_x4 :: emit_sme2_st1b_x4_z_p_m
|
|
inst_sme2_st1h_x4 :: inst_sme2_st1h_x4_z_p_m
|
|
emit_sme2_st1h_x4 :: emit_sme2_st1h_x4_z_p_m
|
|
inst_sme2_st1w_x4 :: inst_sme2_st1w_x4_z_p_m
|
|
emit_sme2_st1w_x4 :: emit_sme2_st1w_x4_z_p_m
|
|
inst_sme2_st1d_x4 :: inst_sme2_st1d_x4_z_p_m
|
|
emit_sme2_st1d_x4 :: emit_sme2_st1d_x4_z_p_m
|
|
inst_sme2_zip_3 :: inst_sme2_zip_3_z_z_z
|
|
emit_sme2_zip_3 :: emit_sme2_zip_3_z_z_z
|
|
inst_sme2_zip_4 :: inst_sme2_zip_4_z_z
|
|
emit_sme2_zip_4 :: emit_sme2_zip_4_z_z
|
|
inst_sme2_uzp_3 :: inst_sme2_uzp_3_z_z_z
|
|
emit_sme2_uzp_3 :: emit_sme2_uzp_3_z_z_z
|
|
inst_sme2_uzp_4 :: inst_sme2_uzp_4_z_z
|
|
emit_sme2_uzp_4 :: emit_sme2_uzp_4_z_z
|
|
inst_tlbi_rpalos :: inst_tlbi_rpalos_r
|
|
emit_tlbi_rpalos :: emit_tlbi_rpalos_r
|
|
inst_tlbi_rpaos :: inst_tlbi_rpaos_r
|
|
emit_tlbi_rpaos :: emit_tlbi_rpaos_r
|
|
inst_at_s1e1a :: inst_at_s1e1a_r
|
|
emit_at_s1e1a :: emit_at_s1e1a_r
|
|
inst_dc_cipapa :: inst_dc_cipapa_r
|
|
emit_dc_cipapa :: emit_dc_cipapa_r
|
|
inst_dc_cigdpapa :: inst_dc_cigdpapa_r
|
|
emit_dc_cigdpapa :: emit_dc_cigdpapa_r
|
|
inst_tlbi_paall :: inst_tlbi_paall_none
|
|
emit_tlbi_paall :: emit_tlbi_paall_none
|
|
inst_tlbi_paallos :: inst_tlbi_paallos_none
|
|
emit_tlbi_paallos :: emit_tlbi_paallos_none
|
|
inst_amx_ldx :: inst_amx_ldx_r
|
|
emit_amx_ldx :: emit_amx_ldx_r
|
|
inst_amx_ldy :: inst_amx_ldy_r
|
|
emit_amx_ldy :: emit_amx_ldy_r
|
|
inst_amx_stx :: inst_amx_stx_r
|
|
emit_amx_stx :: emit_amx_stx_r
|
|
inst_amx_sty :: inst_amx_sty_r
|
|
emit_amx_sty :: emit_amx_sty_r
|
|
inst_amx_ldz :: inst_amx_ldz_r
|
|
emit_amx_ldz :: emit_amx_ldz_r
|
|
inst_amx_stz :: inst_amx_stz_r
|
|
emit_amx_stz :: emit_amx_stz_r
|
|
inst_amx_ldzi :: inst_amx_ldzi_r
|
|
emit_amx_ldzi :: emit_amx_ldzi_r
|
|
inst_amx_stzi :: inst_amx_stzi_r
|
|
emit_amx_stzi :: emit_amx_stzi_r
|
|
inst_amx_extrx :: inst_amx_extrx_r
|
|
emit_amx_extrx :: emit_amx_extrx_r
|
|
inst_amx_extry :: inst_amx_extry_r
|
|
emit_amx_extry :: emit_amx_extry_r
|
|
inst_amx_fma64 :: inst_amx_fma64_r
|
|
emit_amx_fma64 :: emit_amx_fma64_r
|
|
inst_amx_fms64 :: inst_amx_fms64_r
|
|
emit_amx_fms64 :: emit_amx_fms64_r
|
|
inst_amx_fma32 :: inst_amx_fma32_r
|
|
emit_amx_fma32 :: emit_amx_fma32_r
|
|
inst_amx_fms32 :: inst_amx_fms32_r
|
|
emit_amx_fms32 :: emit_amx_fms32_r
|
|
inst_amx_mac16 :: inst_amx_mac16_r
|
|
emit_amx_mac16 :: emit_amx_mac16_r
|
|
inst_amx_fma16 :: inst_amx_fma16_r
|
|
emit_amx_fma16 :: emit_amx_fma16_r
|
|
inst_amx_fms16 :: inst_amx_fms16_r
|
|
emit_amx_fms16 :: emit_amx_fms16_r
|
|
inst_amx_set :: inst_amx_set_none
|
|
emit_amx_set :: emit_amx_set_none
|
|
inst_amx_clr :: inst_amx_clr_none
|
|
emit_amx_clr :: emit_amx_clr_none
|
|
inst_amx_vecint :: inst_amx_vecint_r
|
|
emit_amx_vecint :: emit_amx_vecint_r
|
|
inst_amx_vecfp :: inst_amx_vecfp_r
|
|
emit_amx_vecfp :: emit_amx_vecfp_r
|
|
inst_amx_matint :: inst_amx_matint_r
|
|
emit_amx_matint :: emit_amx_matint_r
|
|
inst_amx_matfp :: inst_amx_matfp_r
|
|
emit_amx_matfp :: emit_amx_matfp_r
|
|
inst_amx_genlut :: inst_amx_genlut_r
|
|
emit_amx_genlut :: emit_amx_genlut_r
|
|
inst_cpyp :: inst_cpyp_r_r_r
|
|
emit_cpyp :: emit_cpyp_r_r_r
|
|
inst_cpym :: inst_cpym_r_r_r
|
|
emit_cpym :: emit_cpym_r_r_r
|
|
inst_cpye :: inst_cpye_r_r_r
|
|
emit_cpye :: emit_cpye_r_r_r
|
|
inst_cpyfp :: inst_cpyfp_r_r_r
|
|
emit_cpyfp :: emit_cpyfp_r_r_r
|
|
inst_cpyfm :: inst_cpyfm_r_r_r
|
|
emit_cpyfm :: emit_cpyfm_r_r_r
|
|
inst_cpyfe :: inst_cpyfe_r_r_r
|
|
emit_cpyfe :: emit_cpyfe_r_r_r
|
|
inst_setp :: inst_setp_r_r_r
|
|
emit_setp :: emit_setp_r_r_r
|
|
inst_setm :: inst_setm_r_r_r
|
|
emit_setm :: emit_setm_r_r_r
|
|
inst_sete :: inst_sete_r_r_r
|
|
emit_sete :: emit_sete_r_r_r
|
|
inst_dc_ivac :: inst_dc_ivac_r
|
|
emit_dc_ivac :: emit_dc_ivac_r
|
|
inst_dc_isw :: inst_dc_isw_r
|
|
emit_dc_isw :: emit_dc_isw_r
|
|
inst_dc_csw :: inst_dc_csw_r
|
|
emit_dc_csw :: emit_dc_csw_r
|
|
inst_dc_cisw :: inst_dc_cisw_r
|
|
emit_dc_cisw :: emit_dc_cisw_r
|
|
inst_dc_zva :: inst_dc_zva_r
|
|
emit_dc_zva :: emit_dc_zva_r
|
|
inst_dc_cvac :: inst_dc_cvac_r
|
|
emit_dc_cvac :: emit_dc_cvac_r
|
|
inst_dc_cvau :: inst_dc_cvau_r
|
|
emit_dc_cvau :: emit_dc_cvau_r
|
|
inst_dc_civac :: inst_dc_civac_r
|
|
emit_dc_civac :: emit_dc_civac_r
|
|
inst_ic_ialluis :: inst_ic_ialluis_none
|
|
emit_ic_ialluis :: emit_ic_ialluis_none
|
|
inst_ic_iallu :: inst_ic_iallu_none
|
|
emit_ic_iallu :: emit_ic_iallu_none
|
|
inst_ic_ivau :: inst_ic_ivau_r
|
|
emit_ic_ivau :: emit_ic_ivau_r
|
|
inst_at_s1e1r :: inst_at_s1e1r_r
|
|
emit_at_s1e1r :: emit_at_s1e1r_r
|
|
inst_at_s1e1w :: inst_at_s1e1w_r
|
|
emit_at_s1e1w :: emit_at_s1e1w_r
|
|
inst_at_s1e0r :: inst_at_s1e0r_r
|
|
emit_at_s1e0r :: emit_at_s1e0r_r
|
|
inst_at_s1e0w :: inst_at_s1e0w_r
|
|
emit_at_s1e0w :: emit_at_s1e0w_r
|
|
inst_at_s1e2r :: inst_at_s1e2r_r
|
|
emit_at_s1e2r :: emit_at_s1e2r_r
|
|
inst_at_s1e2w :: inst_at_s1e2w_r
|
|
emit_at_s1e2w :: emit_at_s1e2w_r
|
|
inst_at_s1e3r :: inst_at_s1e3r_r
|
|
emit_at_s1e3r :: emit_at_s1e3r_r
|
|
inst_at_s1e3w :: inst_at_s1e3w_r
|
|
emit_at_s1e3w :: emit_at_s1e3w_r
|
|
inst_at_s12e1r :: inst_at_s12e1r_r
|
|
emit_at_s12e1r :: emit_at_s12e1r_r
|
|
inst_at_s12e1w :: inst_at_s12e1w_r
|
|
emit_at_s12e1w :: emit_at_s12e1w_r
|
|
inst_at_s12e0r :: inst_at_s12e0r_r
|
|
emit_at_s12e0r :: emit_at_s12e0r_r
|
|
inst_at_s12e0w :: inst_at_s12e0w_r
|
|
emit_at_s12e0w :: emit_at_s12e0w_r
|
|
inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none
|
|
emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none
|
|
inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none
|
|
emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none
|
|
inst_tlbi_vae1 :: inst_tlbi_vae1_r
|
|
emit_tlbi_vae1 :: emit_tlbi_vae1_r
|
|
inst_tlbi_vae1is :: inst_tlbi_vae1is_r
|
|
emit_tlbi_vae1is :: emit_tlbi_vae1is_r
|
|
inst_tlbi_aside1 :: inst_tlbi_aside1_r
|
|
emit_tlbi_aside1 :: emit_tlbi_aside1_r
|
|
inst_tlbi_aside1is :: inst_tlbi_aside1is_r
|
|
emit_tlbi_aside1is :: emit_tlbi_aside1is_r
|
|
inst_tlbi_vaae1 :: inst_tlbi_vaae1_r
|
|
emit_tlbi_vaae1 :: emit_tlbi_vaae1_r
|
|
inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r
|
|
emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r
|
|
inst_tlbi_vale1 :: inst_tlbi_vale1_r
|
|
emit_tlbi_vale1 :: emit_tlbi_vale1_r
|
|
inst_tlbi_vale1is :: inst_tlbi_vale1is_r
|
|
emit_tlbi_vale1is :: emit_tlbi_vale1is_r
|
|
inst_tlbi_vaale1 :: inst_tlbi_vaale1_r
|
|
emit_tlbi_vaale1 :: emit_tlbi_vaale1_r
|
|
inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r
|
|
emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r
|
|
inst_tlbi_alle1 :: inst_tlbi_alle1_none
|
|
emit_tlbi_alle1 :: emit_tlbi_alle1_none
|
|
inst_tlbi_alle1is :: inst_tlbi_alle1is_none
|
|
emit_tlbi_alle1is :: emit_tlbi_alle1is_none
|
|
inst_tlbi_alle2 :: inst_tlbi_alle2_none
|
|
emit_tlbi_alle2 :: emit_tlbi_alle2_none
|
|
inst_tlbi_alle2is :: inst_tlbi_alle2is_none
|
|
emit_tlbi_alle2is :: emit_tlbi_alle2is_none
|
|
inst_tlbi_alle3 :: inst_tlbi_alle3_none
|
|
emit_tlbi_alle3 :: emit_tlbi_alle3_none
|
|
inst_tlbi_alle3is :: inst_tlbi_alle3is_none
|
|
emit_tlbi_alle3is :: emit_tlbi_alle3is_none
|
|
inst_prfm :: inst_prfm_i_m
|
|
emit_prfm :: emit_prfm_i_m
|
|
inst_prfum :: inst_prfum_i_m
|
|
emit_prfum :: emit_prfum_i_m
|
|
inst_prfm_lit :: inst_prfm_lit_i_l
|
|
emit_prfm_lit :: emit_prfm_lit_i_l
|
|
inst_mov_reg :: inst_mov_reg_r_r
|
|
emit_mov_reg :: emit_mov_reg_r_r
|
|
inst_mov_bitmask :: inst_mov_bitmask_r_i
|
|
emit_mov_bitmask :: emit_mov_bitmask_r_i
|
|
inst_mvn :: inst_mvn_r_r
|
|
emit_mvn :: emit_mvn_r_r
|
|
inst_neg_sr :: inst_neg_sr_r_sh
|
|
emit_neg_sr :: emit_neg_sr_r_sh
|
|
inst_negs :: inst_negs_r_sh
|
|
emit_negs :: emit_negs_r_sh
|
|
inst_cmp_sr :: inst_cmp_sr_r_sh
|
|
emit_cmp_sr :: emit_cmp_sr_r_sh
|
|
inst_cmp_er :: inst_cmp_er_r_ex
|
|
emit_cmp_er :: emit_cmp_er_r_ex
|
|
inst_cmp_imm :: inst_cmp_imm_r_i
|
|
emit_cmp_imm :: emit_cmp_imm_r_i
|
|
inst_cmn_sr :: inst_cmn_sr_r_sh
|
|
emit_cmn_sr :: emit_cmn_sr_r_sh
|
|
inst_cmn_er :: inst_cmn_er_r_ex
|
|
emit_cmn_er :: emit_cmn_er_r_ex
|
|
inst_cmn_imm :: inst_cmn_imm_r_i
|
|
emit_cmn_imm :: emit_cmn_imm_r_i
|
|
inst_tst_sr :: inst_tst_sr_r_sh
|
|
emit_tst_sr :: emit_tst_sr_r_sh
|
|
|
|
// Aliases: redundant SME names -> canonical tile/MOVA builders.
|
|
inst_sme_ld1b_za :: inst_sme_ld1b_tile
|
|
emit_sme_ld1b_za :: emit_sme_ld1b_tile
|
|
inst_sme_ld1h_za :: inst_sme_ld1h_tile
|
|
emit_sme_ld1h_za :: emit_sme_ld1h_tile
|
|
inst_sme_ld1w_za :: inst_sme_ld1w_tile
|
|
emit_sme_ld1w_za :: emit_sme_ld1w_tile
|
|
inst_sme_ld1d_za :: inst_sme_ld1d_tile
|
|
emit_sme_ld1d_za :: emit_sme_ld1d_tile
|
|
inst_sme_ld1q_za :: inst_sme_ld1q_tile
|
|
emit_sme_ld1q_za :: emit_sme_ld1q_tile
|
|
inst_sme_st1b_za :: inst_sme_st1b_tile
|
|
emit_sme_st1b_za :: emit_sme_st1b_tile
|
|
inst_sme_st1h_za :: inst_sme_st1h_tile
|
|
emit_sme_st1h_za :: emit_sme_st1h_tile
|
|
inst_sme_st1w_za :: inst_sme_st1w_tile
|
|
emit_sme_st1w_za :: emit_sme_st1w_tile
|
|
inst_sme_st1d_za :: inst_sme_st1d_tile
|
|
emit_sme_st1d_za :: emit_sme_st1d_tile
|
|
inst_sme_st1q_za :: inst_sme_st1q_tile
|
|
emit_sme_st1q_za :: emit_sme_st1q_tile
|
|
inst_sme_mova_to_z :: inst_sme_mova_z_from_tile
|
|
emit_sme_mova_to_z :: emit_sme_mova_z_from_tile
|
|
inst_sme_mova_to_za :: inst_sme_mova_tile_from_z
|
|
emit_sme_mova_to_za :: emit_sme_mova_tile_from_z
|