gingerBill de8c0dc4fe Fix register width test for risc-v, and improve operand slot type inference for risc-v

2026-08-21 00:38:34 +01:00

..

arm32

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

arm64

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

mips

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

mos6502

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

mos65816

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

ppc

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

ppc_vle

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

riscv

Fix register width test for risc-v, and improve operand slot type inference for risc-v

2026-08-21 00:38:34 +01:00

rsp

rexcode/isa: display-side label naming — address order, offset-keyed names

2026-08-03 20:52:11 -04:00

x86

Fix register width test for risc-v, and improve operand slot type inference for risc-v

2026-08-21 00:38:34 +01:00

label_infer.odin

Load rexcode encode/decode tables from committed binary blobs

2026-06-15 07:43:29 -04:00

labels.odin

Load rexcode encode/decode tables from committed binary blobs

2026-06-15 07:43:29 -04:00

print.odin

Remove use of do

2026-08-18 18:23:42 +01:00

status.odin

Replace -> isa.Result with -> (byte_code: u32, ok: bool)

2026-06-15 21:43:58 +01:00