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VSHLL's widest form shifts by exactly the element size. No field holds that amount -- the size is a fixed bit of the form, so the shift is too -- and the form printed no shift at all, which reads as a different instruction. VCADD and VCMLA name their rotation in degrees, 90 and 270 for one and all four quadrants for the other; both printed the raw field, so every rotation read as `#0`. VSEL is an unconditional word that still names a condition, in bits 21:20 and spelled on the mnemonic; it printed a bare `#0` operand instead and no condition. Only four conditions can be named and not in their usual order, so they get a small table. The shift amount had five bits, which cannot hold 32 -- the amount LSR and ASR reach through a zero field. It silently wrapped back to zero, which is why the previous commit's fix for those did not take. Memory had a spare bit and the register operand had two. Three forms were shaped wrong outright. VDUP from a GPR puts Vd in bits 19:16 with D at bit 7, not where NEON usually puts it, so it named a register sixteen too high. VCVTA, VCVTN, VCVTP and VCVTM to a 32-bit integer land in an S register whatever the source width, and the F64 forms had them landing in a D. VFMAL and VFMSL multiply pairs of half-precision values, so their sources are half the width of the destination -- S registers into a D, D registers into a Q -- and they carried no data type at all. VJCVT likewise: it converts F64 to a signed 32-bit integer. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA