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rexcode/arm64: NEON pairwise + variable-shift encode forms

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Adds 9 register-only three-same mnemonics (59 forms) via specgen: ADDP/SMAXP/SMINP/UMAXP/UMINP (pairwise) and SSHL/USHL/SRSHL/URSHL (per-lane variable shift). Verified: decode round-trips (ADDP/SSHL/SMAXP/URSHL), arm64 check + 461 tests pass.

Skipped the already-implemented logical/compare/mul forms (AND_V/ORR_V/EOR_V/BIC_V/ORN_V/BSL/BIT/BIF/CMEQ/CMGT/CMHI/MUL_V) to avoid duplicate keys.
This commit is contained in:
Brendan Punsky
2026-06-15 13:01:26 -04:00
committed by Flāvius
parent d83065e3b8
commit 00b666bbc0
9 changed files with 1093 additions and 851 deletions
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36
core/rexcode/arm64/mnemonic_builders.odin
View File

@@ -779,6 +779,16 @@ inst_saba_r_r_r :: #force_inline proc "contextless" (dst: Regist
emit_saba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_r_r_r(dst, src, src2)) }
inst_uaba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_uaba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_r_r_r(dst, src, src2)) }
inst_addp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_addp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v_r_r_r(dst, src, src2)) }
inst_smaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_smaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_r_r_r(dst, src, src2)) }
inst_umaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_umaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_r_r_r(dst, src, src2)) }
inst_sminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_sminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_r_r_r(dst, src, src2)) }
inst_uminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_uminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_r_r_r(dst, src, src2)) }
inst_sqdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
emit_sqdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_r_r_r(dst, src, src2)) }
inst_sqrdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} }
@@ -827,6 +837,14 @@ inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Regist
emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) }
inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} }
emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) }
inst_srshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_srshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_r_r_r(dst, src, src2)) }
inst_urshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_urshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_r_r_r(dst, src, src2)) }
inst_sshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_sshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_r_r_r(dst, src, src2)) }
inst_ushl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} }
emit_ushl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_r_r_r(dst, src, src2)) }
inst_not_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
emit_not_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_r_r(dst, src)) }
inst_rbit_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} }
@@ -2412,6 +2430,16 @@ inst_saba :: inst_saba_r_r_r
emit_saba :: emit_saba_r_r_r
inst_uaba :: inst_uaba_r_r_r
emit_uaba :: emit_uaba_r_r_r
inst_addp_v :: inst_addp_v_r_r_r
emit_addp_v :: emit_addp_v_r_r_r
inst_smaxp :: inst_smaxp_r_r_r
emit_smaxp :: emit_smaxp_r_r_r
inst_umaxp :: inst_umaxp_r_r_r
emit_umaxp :: emit_umaxp_r_r_r
inst_sminp :: inst_sminp_r_r_r
emit_sminp :: emit_sminp_r_r_r
inst_uminp :: inst_uminp_r_r_r
emit_uminp :: emit_uminp_r_r_r
inst_sqdmulh :: inst_sqdmulh_r_r_r
emit_sqdmulh :: emit_sqdmulh_r_r_r
inst_sqrdmulh :: inst_sqrdmulh_r_r_r
@@ -2460,6 +2488,14 @@ inst_bif :: inst_bif_r_r_r
emit_bif :: emit_bif_r_r_r
inst_bsl :: inst_bsl_r_r_r
emit_bsl :: emit_bsl_r_r_r
inst_srshl :: inst_srshl_r_r_r
emit_srshl :: emit_srshl_r_r_r
inst_urshl :: inst_urshl_r_r_r
emit_urshl :: emit_urshl_r_r_r
inst_sshl :: inst_sshl_r_r_r
emit_sshl :: emit_sshl_r_r_r
inst_ushl :: inst_ushl_r_r_r
emit_ushl :: emit_ushl_r_r_r
inst_not_v :: inst_not_v_r_r
emit_not_v :: emit_not_v_r_r
inst_rbit_v :: inst_rbit_v_r_r

77
core/rexcode/arm64/tablegen/encoding_table.odin
View File

@@ -3182,6 +3182,83 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}},
{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}},
},
.ADDP_V = {
{.ADDP_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}},
{.ADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}},
},
.SMAXP = {
{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}},
{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}},
{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}},
{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}},
{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}},
{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}},
},
.SMINP = {
{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}},
{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}},
{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}},
{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}},
{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}},
{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}},
},
.UMAXP = {
{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}},
{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}},
{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}},
{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}},
{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}},
{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}},
},
.UMINP = {
{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}},
{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}},
{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}},
{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}},
{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}},
{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}},
},
.SSHL = {
{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}},
{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}},
},
.USHL = {
{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}},
{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}},
},
.SRSHL = {
{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}},
{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}},
},
.URSHL = {
{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}},
{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}},
},
// Advanced SIMD two-register misc.
.NOT_V = {

359
core/rexcode/arm64/tablegen/generated/decode_tables.odin
View File

@@ -8,7 +8,7 @@ package rexcode_arm64_generated
import lib "../.."
@(rodata)
DECODE_ENTRIES := [1389]lib.Decode_Entry{
DECODE_ENTRIES := [1448]lib.Decode_Entry{
{ .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} },
{ .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} },
{ .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} },
@@ -60,8 +60,8 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SME_FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} },
{ .SME_BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} },
{ .SME_BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} },
{ .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} },
{ .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} },
{ .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} },
{ .SME_SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} },
{ .SME_SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} },
{ .SME_UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} },
@@ -93,13 +93,13 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} },
{ .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} },
{ .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} },
{ .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} },
{ .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} },
{ .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} },
{ .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} },
{ .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} },
{ .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} },
{ .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} },
{ .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} },
{ .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} },
{ .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} },
{ .SVE_AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} },
{ .SME_RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} },
@@ -117,35 +117,35 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} },
{ .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} },
{ .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} },
{ .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} },
{ .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} },
{ .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} },
{ .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} },
{ .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} },
{ .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} },
{ .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} },
{ .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} },
@@ -155,53 +155,53 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} },
{ .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} },
{ .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} },
{ .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} },
{ .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} },
{ .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} },
{ .SVE_SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} },
{ .SVE_TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} },
{ .SVE_TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} },
{ .SVE_HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} },
@@ -246,25 +246,25 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_BICS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} },
{ .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} },
{ .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} },
{ .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} },
{ .SVE_LDR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} },
{ .SVE_STR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} },
@@ -274,137 +274,137 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} },
{ .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} },
{ .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} },
{ .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} },
{ .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} },
{ .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} },
{ .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} },
{ .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} },
{ .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} },
{ .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} },
{ .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} },
{ .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} },
{ .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} },
{ .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} },
{ .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} },
{ .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} },
{ .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} },
{ .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} },
{ .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} },
{ .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} },
{ .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} },
{ .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} },
{ .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} },
{ .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} },
{ .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} },
{ .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} },
{ .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} },
{ .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} },
{ .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} },
{ .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} },
{ .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} },
{ .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} },
{ .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} },
{ .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} },
{ .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} },
{ .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} },
{ .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} },
{ .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} },
{ .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} },
{ .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} },
{ .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} },
{ .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} },
{ .SVE_LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} },
{ .SVE_LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} },
@@ -422,8 +422,8 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SVE_LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} },
{ .SVE_LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} },
{ .SVE_LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} },
{ .SVE_HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} },
{ .SVE_HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} },
{ .SVE_HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} },
{ .SVE_PRFB, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} },
{ .SVE_PRFH, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} },
{ .SVE_PRFW, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} },
@@ -539,24 +539,24 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .STNP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} },
{ .STNP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} },
{ .STGP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} },
{ .MOV_REG, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} },
{ .MOV_REG, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} },
{ .MOV_REG, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} },
{ .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} },
{ .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} },
{ .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} },
{ .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} },
{ .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} },
{ .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} },
{ .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} },
{ .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} },
{ .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} },
{ .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} },
{ .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} },
{ .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} },
{ .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} },
{ .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} },
{ .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} },
{ .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} },
{ .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} },
{ .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} },
{ .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} },
{ .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} },
{ .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} },
{ .ADD_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} },
{ .ADDS_ER, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} },
@@ -593,8 +593,8 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .ST1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} },
{ .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} },
{ .LD1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} },
{ .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} },
{ .ST1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} },
{ .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} },
{ .LD1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} },
{ .ST1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} },
{ .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {} },
@@ -605,38 +605,38 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} },
{ .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} },
{ .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} },
{ .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} },
{ .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} },
{ .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} },
{ .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} },
{ .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} },
{ .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} },
{ .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} },
{ .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} },
{ .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} },
{ .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} },
{ .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} },
{ .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} },
{ .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} },
{ .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} },
{ .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} },
{ .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} },
{ .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} },
{ .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} },
{ .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} },
{ .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} },
{ .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} },
{ .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} },
{ .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} },
{ .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} },
@@ -794,9 +794,40 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {} },
{ .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {} },
{ .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {} },
{ .ADDP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {} },
{ .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {} },
{ .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {} },
{ .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {} },
{ .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {} },
{ .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {} },
{ .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {} },
{ .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {} },
@@ -806,51 +837,51 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {} },
{ .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {} },
{ .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {} },
{ .FADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} },
{ .FADD_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} },
{ .FADD_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} },
{ .FADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} },
{ .FSUB_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} },
{ .FSUB_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} },
{ .FSUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} },
{ .FMUL_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} },
{ .FSUB_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} },
{ .FMUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} },
{ .FMUL_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} },
{ .FMUL_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} },
{ .FDIV_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} },
{ .FDIV_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} },
{ .FDIV_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} },
{ .FMLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} },
{ .FMLA_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {} },
{ .FMLS_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} },
{ .FMLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} },
{ .FMLS_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {} },
{ .FMLS_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} },
{ .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {} },
{ .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {} },
{ .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {} },
{ .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {} },
{ .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {} },
{ .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {} },
{ .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {} },
{ .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {} },
{ .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {} },
{ .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {} },
{ .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {} },
{ .AND_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} },
{ .ORR_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} },
{ .EOR_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} },
@@ -859,8 +890,36 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {} },
{ .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} },
{ .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} },
{ .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {} },
{ .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {} },
{ .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} },
{ .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} },
{ .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} },
{ .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} },
{ .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} },
{ .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {} },
{ .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} },
{ .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} },
@@ -899,10 +958,10 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} },
{ .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} },
{ .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} },
{ .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} },
{ .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} },
{ .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} },
{ .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} },
{ .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} },
{ .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} },
{ .TST_IMM, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} },
{ .MOV_BITMASK, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} },
{ .TST_IMM, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} },
@@ -1163,8 +1222,8 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .STZGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} },
{ .LDAPUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} },
{ .LDAPUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} },
{ .STLUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} },
{ .STLUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} },
{ .STLUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} },
{ .LDAPURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} },
{ .STLURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {} },
{ .LDAPURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {} },
@@ -1256,14 +1315,14 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {} },
{ .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {} },
{ .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} },
{ .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} },
{ .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} },
{ .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} },
{ .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} },
{ .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} },
{ .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} },
{ .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} },
{ .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} },
{ .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} },
{ .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} },
{ .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} },
{ .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} },
{ .CCMP_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} },
{ .CCMN_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} },
@@ -1289,14 +1348,14 @@ DECODE_ENTRIES := [1389]lib.Decode_Entry{
{ .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true} },
{ .LDR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} },
{ .LDR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} },
{ .LDR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} },
{ .LDR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} },
{ .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} },
{ .LDR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} },
{ .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} },
{ .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} },
{ .STR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} },
{ .STR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} },
{ .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} },
{ .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} },
{ .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} },
{ .FMOV_REG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} },
{ .FMOV_REG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} },
{ .FMOV_GEN, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} },
@@ -1407,14 +1466,14 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{
0x04 = { 454, 76},
0x05 = { 530, 50},
0x06 = { 580, 8},
0x07 = { 588, 280},
0x08 = { 868, 16},
0x09 = { 884, 34},
0x0A = { 918, 98},
0x0B = {1016, 21},
0x0C = {1037, 150},
0x0D = {1187, 88},
0x0E = {1275, 13},
0x0F = {1288, 101},
0x07 = { 588, 339},
0x08 = { 927, 16},
0x09 = { 943, 34},
0x0A = { 977, 98},
0x0B = {1075, 21},
0x0C = {1096, 150},
0x0D = {1246, 88},
0x0E = {1334, 13},
0x0F = {1347, 101},
}

1470
core/rexcode/arm64/tablegen/generated/encode_tables.odin
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2
core/rexcode/arm64/tablegen/specgen.lua
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@@ -49,6 +49,8 @@ local FAMILIES = {
{"MLA_V","mla"}, {"MLS_V","mls"},
{"CMGE","cmge"}, {"CMHS","cmhs"}, {"CMTST","cmtst"},
{"SQDMULH","sqdmulh"}, {"SQRDMULH","sqrdmulh"},
{"ADDP_V","addp"}, {"SMAXP","smaxp"}, {"SMINP","sminp"}, {"UMAXP","umaxp"}, {"UMINP","uminp"},
{"SSHL","sshl"}, {"USHL","ushl"}, {"SRSHL","srshl"}, {"URSHL","urshl"},
}},
{ shape="TWO_SAME", feature="NEON", title="Advanced SIMD two-register misc", items = {
{"NOT_V","not"}, {"RBIT_V","rbit"},

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core/rexcode/arm64/tables/arm64.encode_forms.bin
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core/rexcode/arm64/tables/arm64.encode_runs.bin
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core/rexcode/arm64/tables/arm64.entries.bin
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core/rexcode/arm64/tables/arm64.idx_op0.bin
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