mirrors/Odin
1
0
Fork 0
mirror of https://github.com/odin-lang/Odin.git synced 2026-09-02 02:03:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

rexcode/arm32: VSUDOT has no vector form

Browse Source 
It exists only by element -- the entry for a Q-register multiplier
named a word that is not an encoding.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
2026-08-29 02:05:42 -04:00
committed by Flāvius
parent e02e687dae
commit 5159094cc3
14 changed files with 979 additions and 984 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
core/rexcode/isa/arm32/mnemonic_builders.odin
View File

@@ -1092,9 +1092,7 @@ inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, s
emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) }
inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) }
inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
inst_vsudot_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) }
emit_vsudot_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_q_q_dlane(dst, src, src2, lane)) }
inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
inst_vusdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
@@ -2301,8 +2299,8 @@ inst_vummla :: inst_vummla_q_q_q
emit_vummla :: emit_vummla_q_q_q
inst_vusmmla :: inst_vusmmla_q_q_q
emit_vusmmla :: emit_vusmmla_q_q_q
inst_vsudot :: proc{ inst_vsudot_q_q_q, inst_vsudot_q_q_dlane }
emit_vsudot :: proc{ emit_vsudot_q_q_q, emit_vsudot_q_q_dlane }
inst_vsudot :: inst_vsudot_q_q_dlane
emit_vsudot :: emit_vsudot_q_q_dlane
inst_vusdot :: proc{ inst_vusdot_d_d_d, inst_vusdot_d_d_dlane }
emit_vusdot :: proc{ emit_vusdot_d_d_d, emit_vusdot_d_d_dlane }
inst_vqabs :: inst_vqabs_q_q

1
core/rexcode/isa/arm32/tablegen/encoding_table.odin
View File

@@ -2899,7 +2899,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// vusdot.s8 d0,d1,d2 = 0xFCA1_0D02 -> base 0xFCA00D00
// vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only)
.VSUDOT = {
{.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {}},
{.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}},
},
.VUSDOT = {

1635
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
View File

File diff suppressed because it is too large Load Diff

319
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
View File

@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1726]lib.Encoding{
ENCODE_FORMS := [1725]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -1994,7 +1994,6 @@ ENCODE_FORMS := [1726]lib.Encoding{
// .VUSMMLA
{ .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} },
// .VSUDOT
{ .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} },
{ .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} },
// .VUSDOT
{ .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} },
@@ -2764,162 +2763,162 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VSMMLA = { 1547, 1},
.VUMMLA = { 1548, 1},
.VUSMMLA = { 1549, 1},
.VSUDOT = { 1550, 2},
.VUSDOT = { 1552, 4},
.VQABS = { 1556, 1},
.VQNEG = { 1557, 1},
.VMOVX = { 1558, 1},
.VINS = { 1559, 1},
.IT = { 1560, 1},
.TT = { 1561, 1},
.TTT = { 1562, 1},
.TTA = { 1563, 1},
.TTAT = { 1564, 1},
.SG = { 1565, 1},
.BXNS = { 1566, 1},
.BLXNS = { 1567, 1},
.PAC = { 1568, 1},
.PACBTI = { 1569, 1},
.AUT = { 1570, 1},
.AUTG = { 1571, 1},
.BTI = { 1572, 1},
.WLS = { 1573, 1},
.WLSTP = { 1574, 1},
.DLS = { 1575, 1},
.DLSTP = { 1576, 1},
.LE = { 1577, 1},
.LETP = { 1578, 1},
.LCTP = { 1579, 1},
.BF = { 1580, 1},
.BFX = { 1581, 1},
.BFL = { 1582, 1},
.BFLX = { 1583, 1},
.BFCSEL = { 1584, 1},
.CX1 = { 1585, 1},
.CX1A = { 1586, 1},
.CX1D = { 1587, 1},
.CX1DA = { 1588, 1},
.CX2 = { 1589, 1},
.CX2A = { 1590, 1},
.CX2D = { 1591, 1},
.CX2DA = { 1592, 1},
.CX3 = { 1593, 1},
.CX3A = { 1594, 1},
.CX3D = { 1595, 1},
.CX3DA = { 1596, 1},
.VCX1 = { 1597, 2},
.VCX1A = { 1599, 2},
.VCX2 = { 1601, 2},
.VCX2A = { 1603, 2},
.VCX3 = { 1605, 2},
.VCX3A = { 1607, 2},
.VPT = { 1609, 1},
.VPST = { 1610, 1},
.VPSEL = { 1611, 1},
.VPNOT = { 1612, 1},
.VCTP = { 1613, 1},
.VADDV = { 1614, 1},
.VADDVA = { 1615, 1},
.VADDLV = { 1616, 1},
.VADDLVA = { 1617, 1},
.VMAXV = { 1618, 1},
.VMAXAV = { 1619, 1},
.VMINV = { 1620, 1},
.VMINAV = { 1621, 1},
.VMAXNMV = { 1622, 1},
.VMAXNMAV = { 1623, 1},
.VMINNMV = { 1624, 1},
.VMINNMAV = { 1625, 1},
.VABAV = { 1626, 1},
.VMLADAV = { 1627, 1},
.VMLADAVA = { 1628, 1},
.VMLADAVX = { 1629, 1},
.VMLADAVAX = { 1630, 1},
.VMLALDAV = { 1631, 1},
.VMLALDAVA = { 1632, 1},
.VMLALDAVX = { 1633, 1},
.VMLALDAVAX = { 1634, 1},
.VMLSDAV = { 1635, 1},
.VMLSDAVA = { 1636, 1},
.VMLSDAVX = { 1637, 1},
.VMLSDAVAX = { 1638, 1},
.VMLSLDAV = { 1639, 1},
.VMLSLDAVA = { 1640, 1},
.VMLSLDAVX = { 1641, 1},
.VMLSLDAVAX = { 1642, 1},
.VRMLALDAVH = { 1643, 1},
.VRMLALDAVHA = { 1644, 1},
.VRMLALDAVHX = { 1645, 1},
.VRMLALDAVHAX = { 1646, 1},
.VRMLSLDAVH = { 1647, 1},
.VRMLSLDAVHA = { 1648, 1},
.VRMLSLDAVHX = { 1649, 1},
.VRMLSLDAVHAX = { 1650, 1},
.VMLAV = { 1651, 1},
.VMLAVA = { 1652, 1},
.VMLSV = { 1653, 1},
.VMLSVA = { 1654, 1},
.VCMUL = { 1655, 1},
.VHCADD = { 1656, 2},
.VBRSR = { 1658, 1},
.VSHLC = { 1659, 1},
.VDDUP = { 1660, 1},
.VIDUP = { 1661, 1},
.VDWDUP = { 1662, 1},
.VIWDUP = { 1663, 1},
.VMOVNB = { 1664, 1},
.VMOVNT = { 1665, 1},
.VQMOVNB = { 1666, 1},
.VQMOVNT = { 1667, 1},
.VQMOVUNB = { 1668, 1},
.VQMOVUNT = { 1669, 1},
.VSHLLB = { 1670, 1},
.VSHLLT = { 1671, 1},
.VMULLB = { 1672, 1},
.VMULLT = { 1673, 1},
.VMLALB = { 1674, 1},
.VMLALT = { 1675, 1},
.VMLSLB = { 1676, 1},
.VMLSLT = { 1677, 1},
.VSHRNB = { 1678, 1},
.VSHRNT = { 1679, 1},
.VRSHRNB = { 1680, 1},
.VRSHRNT = { 1681, 1},
.VQSHRNB = { 1682, 1},
.VQSHRNT = { 1683, 1},
.VQRSHRNB = { 1684, 1},
.VQRSHRNT = { 1685, 1},
.VQSHRUNB = { 1686, 1},
.VQSHRUNT = { 1687, 1},
.VQRSHRUNB = { 1688, 1},
.VQRSHRUNT = { 1689, 1},
.VQDMLADH = { 1690, 1},
.VQDMLADHX = { 1691, 1},
.VQDMLSDH = { 1692, 1},
.VQDMLSDHX = { 1693, 1},
.VQRDMLADH = { 1694, 1},
.VQRDMLADHX = { 1695, 1},
.VQRDMLSDH = { 1696, 1},
.VQRDMLSDHX = { 1697, 1},
.VLDRB = { 1698, 2},
.VLDRH = { 1700, 2},
.VLDRW = { 1702, 2},
.VLDRD = { 1704, 2},
.VSTRB = { 1706, 2},
.VSTRH = { 1708, 2},
.VSTRW = { 1710, 2},
.VSTRD = { 1712, 2},
.VLD20 = { 1714, 1},
.VLD21 = { 1715, 1},
.VLD40 = { 1716, 1},
.VLD41 = { 1717, 1},
.VLD42 = { 1718, 1},
.VLD43 = { 1719, 1},
.VST20 = { 1720, 1},
.VST21 = { 1721, 1},
.VST40 = { 1722, 1},
.VST41 = { 1723, 1},
.VST42 = { 1724, 1},
.VST43 = { 1725, 1},
._COUNT = { 1726, 0},
.VSUDOT = { 1550, 1},
.VUSDOT = { 1551, 4},
.VQABS = { 1555, 1},
.VQNEG = { 1556, 1},
.VMOVX = { 1557, 1},
.VINS = { 1558, 1},
.IT = { 1559, 1},
.TT = { 1560, 1},
.TTT = { 1561, 1},
.TTA = { 1562, 1},
.TTAT = { 1563, 1},
.SG = { 1564, 1},
.BXNS = { 1565, 1},
.BLXNS = { 1566, 1},
.PAC = { 1567, 1},
.PACBTI = { 1568, 1},
.AUT = { 1569, 1},
.AUTG = { 1570, 1},
.BTI = { 1571, 1},
.WLS = { 1572, 1},
.WLSTP = { 1573, 1},
.DLS = { 1574, 1},
.DLSTP = { 1575, 1},
.LE = { 1576, 1},
.LETP = { 1577, 1},
.LCTP = { 1578, 1},
.BF = { 1579, 1},
.BFX = { 1580, 1},
.BFL = { 1581, 1},
.BFLX = { 1582, 1},
.BFCSEL = { 1583, 1},
.CX1 = { 1584, 1},
.CX1A = { 1585, 1},
.CX1D = { 1586, 1},
.CX1DA = { 1587, 1},
.CX2 = { 1588, 1},
.CX2A = { 1589, 1},
.CX2D = { 1590, 1},
.CX2DA = { 1591, 1},
.CX3 = { 1592, 1},
.CX3A = { 1593, 1},
.CX3D = { 1594, 1},
.CX3DA = { 1595, 1},
.VCX1 = { 1596, 2},
.VCX1A = { 1598, 2},
.VCX2 = { 1600, 2},
.VCX2A = { 1602, 2},
.VCX3 = { 1604, 2},
.VCX3A = { 1606, 2},
.VPT = { 1608, 1},
.VPST = { 1609, 1},
.VPSEL = { 1610, 1},
.VPNOT = { 1611, 1},
.VCTP = { 1612, 1},
.VADDV = { 1613, 1},
.VADDVA = { 1614, 1},
.VADDLV = { 1615, 1},
.VADDLVA = { 1616, 1},
.VMAXV = { 1617, 1},
.VMAXAV = { 1618, 1},
.VMINV = { 1619, 1},
.VMINAV = { 1620, 1},
.VMAXNMV = { 1621, 1},
.VMAXNMAV = { 1622, 1},
.VMINNMV = { 1623, 1},
.VMINNMAV = { 1624, 1},
.VABAV = { 1625, 1},
.VMLADAV = { 1626, 1},
.VMLADAVA = { 1627, 1},
.VMLADAVX = { 1628, 1},
.VMLADAVAX = { 1629, 1},
.VMLALDAV = { 1630, 1},
.VMLALDAVA = { 1631, 1},
.VMLALDAVX = { 1632, 1},
.VMLALDAVAX = { 1633, 1},
.VMLSDAV = { 1634, 1},
.VMLSDAVA = { 1635, 1},
.VMLSDAVX = { 1636, 1},
.VMLSDAVAX = { 1637, 1},
.VMLSLDAV = { 1638, 1},
.VMLSLDAVA = { 1639, 1},
.VMLSLDAVX = { 1640, 1},
.VMLSLDAVAX = { 1641, 1},
.VRMLALDAVH = { 1642, 1},
.VRMLALDAVHA = { 1643, 1},
.VRMLALDAVHX = { 1644, 1},
.VRMLALDAVHAX = { 1645, 1},
.VRMLSLDAVH = { 1646, 1},
.VRMLSLDAVHA = { 1647, 1},
.VRMLSLDAVHX = { 1648, 1},
.VRMLSLDAVHAX = { 1649, 1},
.VMLAV = { 1650, 1},
.VMLAVA = { 1651, 1},
.VMLSV = { 1652, 1},
.VMLSVA = { 1653, 1},
.VCMUL = { 1654, 1},
.VHCADD = { 1655, 2},
.VBRSR = { 1657, 1},
.VSHLC = { 1658, 1},
.VDDUP = { 1659, 1},
.VIDUP = { 1660, 1},
.VDWDUP = { 1661, 1},
.VIWDUP = { 1662, 1},
.VMOVNB = { 1663, 1},
.VMOVNT = { 1664, 1},
.VQMOVNB = { 1665, 1},
.VQMOVNT = { 1666, 1},
.VQMOVUNB = { 1667, 1},
.VQMOVUNT = { 1668, 1},
.VSHLLB = { 1669, 1},
.VSHLLT = { 1670, 1},
.VMULLB = { 1671, 1},
.VMULLT = { 1672, 1},
.VMLALB = { 1673, 1},
.VMLALT = { 1674, 1},
.VMLSLB = { 1675, 1},
.VMLSLT = { 1676, 1},
.VSHRNB = { 1677, 1},
.VSHRNT = { 1678, 1},
.VRSHRNB = { 1679, 1},
.VRSHRNT = { 1680, 1},
.VQSHRNB = { 1681, 1},
.VQSHRNT = { 1682, 1},
.VQRSHRNB = { 1683, 1},
.VQRSHRNT = { 1684, 1},
.VQSHRUNB = { 1685, 1},
.VQSHRUNT = { 1686, 1},
.VQRSHRUNB = { 1687, 1},
.VQRSHRUNT = { 1688, 1},
.VQDMLADH = { 1689, 1},
.VQDMLADHX = { 1690, 1},
.VQDMLSDH = { 1691, 1},
.VQDMLSDHX = { 1692, 1},
.VQRDMLADH = { 1693, 1},
.VQRDMLADHX = { 1694, 1},
.VQRDMLSDH = { 1695, 1},
.VQRDMLSDHX = { 1696, 1},
.VLDRB = { 1697, 2},
.VLDRH = { 1699, 2},
.VLDRW = { 1701, 2},
.VLDRD = { 1703, 2},
.VSTRB = { 1705, 2},
.VSTRH = { 1707, 2},
.VSTRW = { 1709, 2},
.VSTRD = { 1711, 2},
.VLD20 = { 1713, 1},
.VLD21 = { 1714, 1},
.VLD40 = { 1715, 1},
.VLD41 = { 1716, 1},
.VLD42 = { 1717, 1},
.VLD43 = { 1718, 1},
.VST20 = { 1719, 1},
.VST21 = { 1720, 1},
.VST40 = { 1721, 1},
.VST41 = { 1722, 1},
.VST42 = { 1723, 1},
.VST43 = { 1724, 1},
._COUNT = { 1725, 0},
}

BIN
core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 11 KiB

After

Width:  |  Height:  |  Size: 11 KiB

BIN
core/rexcode/isa/arm32/tables/arm32.encode_forms.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.encode_runs.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.entries.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.form_idx.bin
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 3.4 KiB

After

Width:  |  Height:  |  Size: 3.4 KiB

BIN
core/rexcode/isa/arm32/tables/arm32.idx_a32.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.idx_t16.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.idx_t32.bin
View File

Binary file not shown.

BIN
core/rexcode/isa/arm32/tables/arm32.idx_t32_sub.bin
View File

Binary file not shown.

2
core/rexcode/isa/arm32/tests/smoke.odin
View File

@@ -505,7 +505,7 @@ run_smoke :: proc() {
check("VUMMLA", .VUMMLA, 0, 0xFC200C50, 0xFFB00F50)
check("VUSMMLA", .VUSMMLA, 0, 0xFCA00C40, 0xFFB00F50)
check("VUSDOT D", .VUSDOT, 0, 0xFCA00D00, 0xFFB00F10)
check("VSUDOT lane", .VSUDOT, 1, 0xFE800D50, 0xFFB00F50)
check("VSUDOT lane", .VSUDOT, 0, 0xFE800D50, 0xFFB00F50)
// ---- Lane-indexed NEON ----
check("VMUL lane D .S16", .VMUL, 18, 0xF2900840, 0xFFB00F50)