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rexcode/arm32: CRC32 is not predicable, VDUP's lane, and p15 is not #15

Browse Source 
CRC32 and its castagnoli variants are unconditional-only: the condition
field is fixed at AL. Their entries left bits 31:28 free, so every
condition decoded as a CRC32 that cannot exist.

VDUP from a lane packs the element size and the lane index into one
four-bit field -- `xxx1` is a byte lane, `xx10` a halfword, `x100` a
word -- and the two forms it had read that field as though it were an
ordinary by-scalar operand, which is a different layout entirely. The
word they named, with the field zero, is not an encoding at all. Six
forms now, two per element size, each with the size in its data type.

A coprocessor number is written `p15`. It had been printing as a plain
`#15`, which is not what an assembler takes, and it is a different kind
of thing from the CRn and CRm registers that were already spelled
`c0` -- so it gets a class of its own rather than sharing theirs.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
2026-08-29 02:04:04 -04:00
committed by Flāvius
parent 93a0baf422
commit e02e687dae
18 changed files with 1306 additions and 1272 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
core/rexcode/isa/arm32/decoder.odin
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@@ -437,7 +437,7 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
case .CPS_IFLAGS: return op_imm(i64(word & 0x1FF))
case .PSR_FIELD_MASK: return op_imm(i64(decode_psr_field(word)))
case .SYSM_FIELD: return op_imm(i64(word & 0xFF))
case .COPROC_NUM_FIELD: return op_imm(i64((word >> 8) & 0xF))
case .COPROC_NUM_FIELD: return op_reg(Register(REG_COPROC_NUM | u16((word >> 8) & 0xF)))
case .COPROC_OPC1_FIELD: return op_imm(i64((word >> 20) & 0xF))
case .COPROC_OPC2_FIELD: return op_imm(i64((word >> 5) & 0x7))
case .COPROC_CRN_FIELD: return op_reg(Register(REG_COPROC | u16((word >> 16) & 0xF)))
@@ -508,6 +508,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask))
op.list = {count = count, stride = 1}
return op
case .NEON_VDUP_LANE_8, .NEON_VDUP_LANE_16, .NEON_VDUP_LANE_32:
imm4 := (word >> 16) & 0xF
shift: u32 = enc == .NEON_VDUP_LANE_8 ? 1 : enc == .NEON_VDUP_LANE_16 ? 2 : 3
return op_dpr_lane(Register(REG_DPR | u16(((word >> 5) & 1) << 4 | (word & 0xF))),
u8(imm4 >> shift))
case .NEON_VM_SCALAR_16:
return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)),
u8(((word >> 5) & 1) << 1 | ((word >> 3) & 1)))

10
core/rexcode/isa/arm32/encoder.odin
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@@ -293,6 +293,9 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op
#partial switch enc {
case .NEON_VM_SCALAR_16: return op.has_lane && reg_hw(op.reg) < 8 && op.lane < 4
case .NEON_VM_SCALAR_32: return op.has_lane && reg_hw(op.reg) < 16 && op.lane < 2
case .NEON_VDUP_LANE_8: return op.has_lane && op.lane < 8
case .NEON_VDUP_LANE_16: return op.has_lane && op.lane < 4
case .NEON_VDUP_LANE_32: return op.has_lane && op.lane < 2
}
return true
case .QPR_ELEM: return op.kind == .REGISTER && is_qpr(op.reg)
@@ -549,6 +552,11 @@ pack_operand_inline :: #force_inline proc(
n := u32(reg_hw(op.reg)) & 0x1F
shift, mask, _ := neon_lane_shape(enc)
return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift
case .NEON_VDUP_LANE_8, .NEON_VDUP_LANE_16, .NEON_VDUP_LANE_32:
n := u32(reg_hw(op.reg)) & 0x1F
shift: u32 = enc == .NEON_VDUP_LANE_8 ? 1 : enc == .NEON_VDUP_LANE_16 ? 2 : 3
// The marker bit below the index is a fixed bit of the form.
return ((n >> 4) & 1) << 5 | (n & 0xF) | (u32(op.lane) << shift) << 16
case .NEON_VM_SCALAR_16:
n := u32(reg_hw(op.reg)) & 0x7
idx := u32(op.lane) & 0x3
@@ -618,7 +626,7 @@ pack_operand_inline :: #force_inline proc(
return ((u32(reg_hw(m.base)) & 0xF) << 16) | (u32(reg_hw(m.index)) & 0xF)
// ---- Coprocessor -------------------------------------------------------
case .COPROC_NUM_FIELD: return (u32(op.immediate) & 0xF) << 8
case .COPROC_NUM_FIELD: return (u32(reg_hw(op.reg)) & 0xF) << 8
case .COPROC_OPC1_FIELD: return (u32(op.immediate) & 0xF) << 20
case .COPROC_OPC2_FIELD: return (u32(op.immediate) & 0x7) << 5
case .COPROC_CRN_FIELD: return (u32(reg_hw(op.reg)) & 0xF) << 16

4
core/rexcode/isa/arm32/encoding_types.odin
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@@ -355,6 +355,10 @@ Operand_Encoding :: enum u8 {
// 2:0, so D0..D7, and the lane from M:bit3; 32-bit takes Vm from bits
// 3:0, so D0..D15, and the lane from M alone.
NEON_VM_SCALAR_16, NEON_VM_SCALAR_32,
// VDUP from a lane packs the element size and the lane index into one
// four-bit field: `xxx1` is a byte lane, `xx10` a halfword, `x100` a
// word, and the bits above the marker are the index.
NEON_VDUP_LANE_8, NEON_VDUP_LANE_16, NEON_VDUP_LANE_32,
// NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list,
// the register count is part of the form's type field at bits 11:8, so the
// encoding writes only Vd; how many registers -- and whether the run steps

2
core/rexcode/isa/arm32/printer.odin
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@@ -501,6 +501,8 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool = fals
}
case REG_COPROC:
fmt.sbprintf(sb, "c%d", hw)
case REG_COPROC_NUM:
fmt.sbprintf(sb, "p%d", hw)
case REG_ENDIAN:
strings.write_string(sb, hw == 0 ? "le" : "be")
case:

3
core/rexcode/isa/arm32/registers.odin
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@@ -38,6 +38,9 @@ REG_COPROC :: u16(0x8000)
// SETEND names its argument `le` or `be`. That is a bare token in the syntax,
// which is what the special-register classes above already model.
REG_ENDIAN :: u16(0x9000)
// A coprocessor number is written `p15`, not as a plain number, and it is a
// different thing from the CRn/CRm registers REG_COPROC names.
REG_COPROC_NUM :: u16(0xA000)
REG_CLASS_MASK :: u16(0xF000)
REG_HW_MASK :: u16(0x0FFF)

20
core/rexcode/isa/arm32/tablegen/encoding_table.odin
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@@ -1277,12 +1277,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// ARMv8 CRC32 family
// cond 0001 0 sz 0 Rn Rd 0000 0 0 1 0 0 Rm sz=00 byte / 01 half / 10 word
// bit 9 selects CRC32 (0) vs CRC32C (1).
.CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {}} },
.CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1000040, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
.CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1200040, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
.CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1400040, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
.CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1000240, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
.CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1200240, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
.CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0xE1400240, 0xFFF00FF0, .CRC32, .A32, {cond_in_28=false}, {}} },
// =========================================================================
@@ -2319,8 +2319,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}},
{.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VN_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}},
// VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm
{.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}},
{.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}},
{.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VDUP_LANE_8, .NONE, .NONE}, 0xF3B10C00, 0xFFB10FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VDUP_LANE_8, .NONE, .NONE}, 0xF3B10C40, 0xFFB10FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VDUP_LANE_16, .NONE, .NONE}, 0xF3B20C00, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
{.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VDUP_LANE_16, .NONE, .NONE}, 0xF3B20C40, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
{.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VDUP_LANE_32, .NONE, .NONE}, 0xF3B40C00, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
{.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VDUP_LANE_32, .NONE, .NONE}, 0xF3B40C40, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
// MVE VDUP Qd, Rt
{.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}},
},

2118
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
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File diff suppressed because it is too large Load Diff

410
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
View File

@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1722]lib.Encoding{
ENCODE_FORMS := [1726]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -887,17 +887,17 @@ ENCODE_FORMS := [1722]lib.Encoding{
// .STC2
{ .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {}, {.NONE,.NONE} },
// .CRC32B
{ .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1000040, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .CRC32H
{ .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1200040, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .CRC32W
{ .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1400040, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .CRC32CB
{ .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1000240, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .CRC32CH
{ .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1200240, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .CRC32CW
{ .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0xE1400240, 0xFFF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
// .VADD
{ .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} },
{ .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} },
@@ -1859,8 +1859,12 @@ ENCODE_FORMS := [1722]lib.Encoding{
// .VDUP
{ .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VN_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} },
{ .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} },
{ .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VDUP_LANE_8,.NONE,.NONE}, 0xF3B10C00, 0xFFB10FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VDUP_LANE_8,.NONE,.NONE}, 0xF3B10C40, 0xFFB10FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VDUP_LANE_16,.NONE,.NONE}, 0xF3B20C00, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VDUP_LANE_16,.NONE,.NONE}, 0xF3B20C40, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VDUP_LANE_32,.NONE,.NONE}, 0xF3B40C00, 0xFFB70FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VDUP_LANE_32,.NONE,.NONE}, 0xF3B40C40, 0xFFB70FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
// .VSWP
{ .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
@@ -2724,198 +2728,198 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VTRN = { 1433, 6},
.VUZP = { 1439, 5},
.VZIP = { 1444, 5},
.VDUP = { 1449, 5},
.VSWP = { 1454, 2},
.VLD1 = { 1456, 8},
.VLD2 = { 1464, 7},
.VLD3 = { 1471, 6},
.VLD4 = { 1477, 6},
.VST1 = { 1483, 7},
.VST2 = { 1490, 6},
.VST3 = { 1496, 5},
.VST4 = { 1501, 5},
.AESE = { 1506, 1},
.AESD = { 1507, 1},
.AESMC = { 1508, 1},
.AESIMC = { 1509, 1},
.SHA1H = { 1510, 1},
.SHA1SU0 = { 1511, 1},
.SHA1SU1 = { 1512, 1},
.SHA1C = { 1513, 1},
.SHA1M = { 1514, 1},
.SHA1P = { 1515, 1},
.SHA256H = { 1516, 1},
.SHA256H2 = { 1517, 1},
.SHA256SU0 = { 1518, 1},
.SHA256SU1 = { 1519, 1},
.VJCVT = { 1520, 1},
.VSDOT = { 1521, 4},
.VUDOT = { 1525, 4},
.VDOT = { 1529, 2},
.VMMLA = { 1531, 1},
.VFMAL = { 1532, 2},
.VFMSL = { 1534, 2},
.VCMLA = { 1536, 5},
.VCADD = { 1541, 2},
.VSMMLA = { 1543, 1},
.VUMMLA = { 1544, 1},
.VUSMMLA = { 1545, 1},
.VSUDOT = { 1546, 2},
.VUSDOT = { 1548, 4},
.VQABS = { 1552, 1},
.VQNEG = { 1553, 1},
.VMOVX = { 1554, 1},
.VINS = { 1555, 1},
.IT = { 1556, 1},
.TT = { 1557, 1},
.TTT = { 1558, 1},
.TTA = { 1559, 1},
.TTAT = { 1560, 1},
.SG = { 1561, 1},
.BXNS = { 1562, 1},
.BLXNS = { 1563, 1},
.PAC = { 1564, 1},
.PACBTI = { 1565, 1},
.AUT = { 1566, 1},
.AUTG = { 1567, 1},
.BTI = { 1568, 1},
.WLS = { 1569, 1},
.WLSTP = { 1570, 1},
.DLS = { 1571, 1},
.DLSTP = { 1572, 1},
.LE = { 1573, 1},
.LETP = { 1574, 1},
.LCTP = { 1575, 1},
.BF = { 1576, 1},
.BFX = { 1577, 1},
.BFL = { 1578, 1},
.BFLX = { 1579, 1},
.BFCSEL = { 1580, 1},
.CX1 = { 1581, 1},
.CX1A = { 1582, 1},
.CX1D = { 1583, 1},
.CX1DA = { 1584, 1},
.CX2 = { 1585, 1},
.CX2A = { 1586, 1},
.CX2D = { 1587, 1},
.CX2DA = { 1588, 1},
.CX3 = { 1589, 1},
.CX3A = { 1590, 1},
.CX3D = { 1591, 1},
.CX3DA = { 1592, 1},
.VCX1 = { 1593, 2},
.VCX1A = { 1595, 2},
.VCX2 = { 1597, 2},
.VCX2A = { 1599, 2},
.VCX3 = { 1601, 2},
.VCX3A = { 1603, 2},
.VPT = { 1605, 1},
.VPST = { 1606, 1},
.VPSEL = { 1607, 1},
.VPNOT = { 1608, 1},
.VCTP = { 1609, 1},
.VADDV = { 1610, 1},
.VADDVA = { 1611, 1},
.VADDLV = { 1612, 1},
.VADDLVA = { 1613, 1},
.VMAXV = { 1614, 1},
.VMAXAV = { 1615, 1},
.VMINV = { 1616, 1},
.VMINAV = { 1617, 1},
.VMAXNMV = { 1618, 1},
.VMAXNMAV = { 1619, 1},
.VMINNMV = { 1620, 1},
.VMINNMAV = { 1621, 1},
.VABAV = { 1622, 1},
.VMLADAV = { 1623, 1},
.VMLADAVA = { 1624, 1},
.VMLADAVX = { 1625, 1},
.VMLADAVAX = { 1626, 1},
.VMLALDAV = { 1627, 1},
.VMLALDAVA = { 1628, 1},
.VMLALDAVX = { 1629, 1},
.VMLALDAVAX = { 1630, 1},
.VMLSDAV = { 1631, 1},
.VMLSDAVA = { 1632, 1},
.VMLSDAVX = { 1633, 1},
.VMLSDAVAX = { 1634, 1},
.VMLSLDAV = { 1635, 1},
.VMLSLDAVA = { 1636, 1},
.VMLSLDAVX = { 1637, 1},
.VMLSLDAVAX = { 1638, 1},
.VRMLALDAVH = { 1639, 1},
.VRMLALDAVHA = { 1640, 1},
.VRMLALDAVHX = { 1641, 1},
.VRMLALDAVHAX = { 1642, 1},
.VRMLSLDAVH = { 1643, 1},
.VRMLSLDAVHA = { 1644, 1},
.VRMLSLDAVHX = { 1645, 1},
.VRMLSLDAVHAX = { 1646, 1},
.VMLAV = { 1647, 1},
.VMLAVA = { 1648, 1},
.VMLSV = { 1649, 1},
.VMLSVA = { 1650, 1},
.VCMUL = { 1651, 1},
.VHCADD = { 1652, 2},
.VBRSR = { 1654, 1},
.VSHLC = { 1655, 1},
.VDDUP = { 1656, 1},
.VIDUP = { 1657, 1},
.VDWDUP = { 1658, 1},
.VIWDUP = { 1659, 1},
.VMOVNB = { 1660, 1},
.VMOVNT = { 1661, 1},
.VQMOVNB = { 1662, 1},
.VQMOVNT = { 1663, 1},
.VQMOVUNB = { 1664, 1},
.VQMOVUNT = { 1665, 1},
.VSHLLB = { 1666, 1},
.VSHLLT = { 1667, 1},
.VMULLB = { 1668, 1},
.VMULLT = { 1669, 1},
.VMLALB = { 1670, 1},
.VMLALT = { 1671, 1},
.VMLSLB = { 1672, 1},
.VMLSLT = { 1673, 1},
.VSHRNB = { 1674, 1},
.VSHRNT = { 1675, 1},
.VRSHRNB = { 1676, 1},
.VRSHRNT = { 1677, 1},
.VQSHRNB = { 1678, 1},
.VQSHRNT = { 1679, 1},
.VQRSHRNB = { 1680, 1},
.VQRSHRNT = { 1681, 1},
.VQSHRUNB = { 1682, 1},
.VQSHRUNT = { 1683, 1},
.VQRSHRUNB = { 1684, 1},
.VQRSHRUNT = { 1685, 1},
.VQDMLADH = { 1686, 1},
.VQDMLADHX = { 1687, 1},
.VQDMLSDH = { 1688, 1},
.VQDMLSDHX = { 1689, 1},
.VQRDMLADH = { 1690, 1},
.VQRDMLADHX = { 1691, 1},
.VQRDMLSDH = { 1692, 1},
.VQRDMLSDHX = { 1693, 1},
.VLDRB = { 1694, 2},
.VLDRH = { 1696, 2},
.VLDRW = { 1698, 2},
.VLDRD = { 1700, 2},
.VSTRB = { 1702, 2},
.VSTRH = { 1704, 2},
.VSTRW = { 1706, 2},
.VSTRD = { 1708, 2},
.VLD20 = { 1710, 1},
.VLD21 = { 1711, 1},
.VLD40 = { 1712, 1},
.VLD41 = { 1713, 1},
.VLD42 = { 1714, 1},
.VLD43 = { 1715, 1},
.VST20 = { 1716, 1},
.VST21 = { 1717, 1},
.VST40 = { 1718, 1},
.VST41 = { 1719, 1},
.VST42 = { 1720, 1},
.VST43 = { 1721, 1},
._COUNT = { 1722, 0},
.VDUP = { 1449, 9},
.VSWP = { 1458, 2},
.VLD1 = { 1460, 8},
.VLD2 = { 1468, 7},
.VLD3 = { 1475, 6},
.VLD4 = { 1481, 6},
.VST1 = { 1487, 7},
.VST2 = { 1494, 6},
.VST3 = { 1500, 5},
.VST4 = { 1505, 5},
.AESE = { 1510, 1},
.AESD = { 1511, 1},
.AESMC = { 1512, 1},
.AESIMC = { 1513, 1},
.SHA1H = { 1514, 1},
.SHA1SU0 = { 1515, 1},
.SHA1SU1 = { 1516, 1},
.SHA1C = { 1517, 1},
.SHA1M = { 1518, 1},
.SHA1P = { 1519, 1},
.SHA256H = { 1520, 1},
.SHA256H2 = { 1521, 1},
.SHA256SU0 = { 1522, 1},
.SHA256SU1 = { 1523, 1},
.VJCVT = { 1524, 1},
.VSDOT = { 1525, 4},
.VUDOT = { 1529, 4},
.VDOT = { 1533, 2},
.VMMLA = { 1535, 1},
.VFMAL = { 1536, 2},
.VFMSL = { 1538, 2},
.VCMLA = { 1540, 5},
.VCADD = { 1545, 2},
.VSMMLA = { 1547, 1},
.VUMMLA = { 1548, 1},
.VUSMMLA = { 1549, 1},
.VSUDOT = { 1550, 2},
.VUSDOT = { 1552, 4},
.VQABS = { 1556, 1},
.VQNEG = { 1557, 1},
.VMOVX = { 1558, 1},
.VINS = { 1559, 1},
.IT = { 1560, 1},
.TT = { 1561, 1},
.TTT = { 1562, 1},
.TTA = { 1563, 1},
.TTAT = { 1564, 1},
.SG = { 1565, 1},
.BXNS = { 1566, 1},
.BLXNS = { 1567, 1},
.PAC = { 1568, 1},
.PACBTI = { 1569, 1},
.AUT = { 1570, 1},
.AUTG = { 1571, 1},
.BTI = { 1572, 1},
.WLS = { 1573, 1},
.WLSTP = { 1574, 1},
.DLS = { 1575, 1},
.DLSTP = { 1576, 1},
.LE = { 1577, 1},
.LETP = { 1578, 1},
.LCTP = { 1579, 1},
.BF = { 1580, 1},
.BFX = { 1581, 1},
.BFL = { 1582, 1},
.BFLX = { 1583, 1},
.BFCSEL = { 1584, 1},
.CX1 = { 1585, 1},
.CX1A = { 1586, 1},
.CX1D = { 1587, 1},
.CX1DA = { 1588, 1},
.CX2 = { 1589, 1},
.CX2A = { 1590, 1},
.CX2D = { 1591, 1},
.CX2DA = { 1592, 1},
.CX3 = { 1593, 1},
.CX3A = { 1594, 1},
.CX3D = { 1595, 1},
.CX3DA = { 1596, 1},
.VCX1 = { 1597, 2},
.VCX1A = { 1599, 2},
.VCX2 = { 1601, 2},
.VCX2A = { 1603, 2},
.VCX3 = { 1605, 2},
.VCX3A = { 1607, 2},
.VPT = { 1609, 1},
.VPST = { 1610, 1},
.VPSEL = { 1611, 1},
.VPNOT = { 1612, 1},
.VCTP = { 1613, 1},
.VADDV = { 1614, 1},
.VADDVA = { 1615, 1},
.VADDLV = { 1616, 1},
.VADDLVA = { 1617, 1},
.VMAXV = { 1618, 1},
.VMAXAV = { 1619, 1},
.VMINV = { 1620, 1},
.VMINAV = { 1621, 1},
.VMAXNMV = { 1622, 1},
.VMAXNMAV = { 1623, 1},
.VMINNMV = { 1624, 1},
.VMINNMAV = { 1625, 1},
.VABAV = { 1626, 1},
.VMLADAV = { 1627, 1},
.VMLADAVA = { 1628, 1},
.VMLADAVX = { 1629, 1},
.VMLADAVAX = { 1630, 1},
.VMLALDAV = { 1631, 1},
.VMLALDAVA = { 1632, 1},
.VMLALDAVX = { 1633, 1},
.VMLALDAVAX = { 1634, 1},
.VMLSDAV = { 1635, 1},
.VMLSDAVA = { 1636, 1},
.VMLSDAVX = { 1637, 1},
.VMLSDAVAX = { 1638, 1},
.VMLSLDAV = { 1639, 1},
.VMLSLDAVA = { 1640, 1},
.VMLSLDAVX = { 1641, 1},
.VMLSLDAVAX = { 1642, 1},
.VRMLALDAVH = { 1643, 1},
.VRMLALDAVHA = { 1644, 1},
.VRMLALDAVHX = { 1645, 1},
.VRMLALDAVHAX = { 1646, 1},
.VRMLSLDAVH = { 1647, 1},
.VRMLSLDAVHA = { 1648, 1},
.VRMLSLDAVHX = { 1649, 1},
.VRMLSLDAVHAX = { 1650, 1},
.VMLAV = { 1651, 1},
.VMLAVA = { 1652, 1},
.VMLSV = { 1653, 1},
.VMLSVA = { 1654, 1},
.VCMUL = { 1655, 1},
.VHCADD = { 1656, 2},
.VBRSR = { 1658, 1},
.VSHLC = { 1659, 1},
.VDDUP = { 1660, 1},
.VIDUP = { 1661, 1},
.VDWDUP = { 1662, 1},
.VIWDUP = { 1663, 1},
.VMOVNB = { 1664, 1},
.VMOVNT = { 1665, 1},
.VQMOVNB = { 1666, 1},
.VQMOVNT = { 1667, 1},
.VQMOVUNB = { 1668, 1},
.VQMOVUNT = { 1669, 1},
.VSHLLB = { 1670, 1},
.VSHLLT = { 1671, 1},
.VMULLB = { 1672, 1},
.VMULLT = { 1673, 1},
.VMLALB = { 1674, 1},
.VMLALT = { 1675, 1},
.VMLSLB = { 1676, 1},
.VMLSLT = { 1677, 1},
.VSHRNB = { 1678, 1},
.VSHRNT = { 1679, 1},
.VRSHRNB = { 1680, 1},
.VRSHRNT = { 1681, 1},
.VQSHRNB = { 1682, 1},
.VQSHRNT = { 1683, 1},
.VQRSHRNB = { 1684, 1},
.VQRSHRNT = { 1685, 1},
.VQSHRUNB = { 1686, 1},
.VQSHRUNT = { 1687, 1},
.VQRSHRUNB = { 1688, 1},
.VQRSHRUNT = { 1689, 1},
.VQDMLADH = { 1690, 1},
.VQDMLADHX = { 1691, 1},
.VQDMLSDH = { 1692, 1},
.VQDMLSDHX = { 1693, 1},
.VQRDMLADH = { 1694, 1},
.VQRDMLADHX = { 1695, 1},
.VQRDMLSDH = { 1696, 1},
.VQRDMLSDHX = { 1697, 1},
.VLDRB = { 1698, 2},
.VLDRH = { 1700, 2},
.VLDRW = { 1702, 2},
.VLDRD = { 1704, 2},
.VSTRB = { 1706, 2},
.VSTRH = { 1708, 2},
.VSTRW = { 1710, 2},
.VSTRD = { 1712, 2},
.VLD20 = { 1714, 1},
.VLD21 = { 1715, 1},
.VLD40 = { 1716, 1},
.VLD41 = { 1717, 1},
.VLD42 = { 1718, 1},
.VLD43 = { 1719, 1},
.VST20 = { 1720, 1},
.VST21 = { 1721, 1},
.VST40 = { 1722, 1},
.VST41 = { 1723, 1},
.VST42 = { 1724, 1},
.VST43 = { 1725, 1},
._COUNT = { 1726, 0},
}

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core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
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core/rexcode/isa/arm32/tables/arm32.encode_forms.bin
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core/rexcode/isa/arm32/tables/arm32.encode_runs.bin
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core/rexcode/isa/arm32/tables/arm32.entries.bin
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core/rexcode/isa/arm32/tables/arm32.form_idx.bin
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core/rexcode/isa/arm32/tables/arm32.idx_a32.bin
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4
core/rexcode/isa/arm32/tests/smoke.odin
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@@ -117,8 +117,8 @@ run_smoke :: proc() {
check("STL (v8)", .STL, 0, 0x0180FC90, 0x0FF0FFF0)
// ---- CRC32 ----
check("CRC32B", .CRC32B, 0, 0x01000040, 0x0FF00FF0)
check("CRC32CW", .CRC32CW, 0, 0x01400240, 0x0FF00FF0)
check("CRC32B", .CRC32B, 0, 0xE1000040, 0xFFF00FF0)
check("CRC32CW", .CRC32CW, 0, 0xE1400240, 0xFFF00FF0)
// ---- VFP scalar ----
check("VADD.F32", .VADD, 0, 0x0E300A00, 0x0FB00B50)