rexcode/arm32: Branch Future BF/BFL/BFLX/BFI_BR encode forms

Reverse-engineered the ARMv8.1-M Branch Future T32 encoding from llvm-mc: bf-point imm4 = (label-(PC+4))/2 at hw0[10:7]; branch target val = (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target is Rm at hw0[3:0]. New REL_BF operand + BF_BOFF/BF_BLOC/BF_RM encodings + BF_BOFF_T32/BF_BLOC_T32 relocations with resolver. BF=0xF040E001, BFL=0xF000C001, BFLX=0xF070E001, BFI_BR=0xF060E001. Tightened the WLSTP/DLSTP masks to mark hw0[6] static (it is always 0 for valid B/H/W/D sizes) so they no longer shadow the BF register forms. Byte-exact vs llvm-mc with resolved bf-point/target offsets; 600 tests green. (BFCSEL still pending -- it adds an else-target + condition.)
2026-06-19 16:42:33 +00:00 · 2026-06-18 04:47:03 -04:00
parent c6edd6d5cd
commit 808716517e
17 changed files with 903 additions and 781 deletions
--- a/core/rexcode/arm32/decoder.odin
+++ b/core/rexcode/arm32/decoder.odin
@@ -464,6 +464,22 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
 		imm5  := (word >> 3) & 0x1F
 		v := (i_bit << 6) | (imm5 << 1)
 		return op_rel_offset(i64(v))
+	// ---- ARMv8.1-M Branch Future ----
+	case .BF_BOFF:
+		imm4 := (word >> 23) & 0xF          // hw0[10:7]
+		return op_rel_offset(i64(imm4) << 1)
+	case .BF_BLOC:
+		j     := (word >> 11) & 1           // hw1[11]
+		imm10 := (word >> 1)  & 0x3FF       // hw1[10:1]
+		val   := (imm10 << 1) | j
+		return op_rel_offset(i64(val) << 1)
+	case .BF_BELSE:
+		imm   := (word >> 23) & 0xF
+		return op_rel_offset(i64(imm) << 1)
+	case .BF_RM:
+		return op_reg(Register(REG_GPR | u16((word >> 16) & 0xF)))
+	case .BFCSEL_COND:
+		return op_imm(i64((word >> 18) & 0xF))

 	// ---- Saturate / bit field ----
 	case .SAT_IMM5, .SAT_IMM5_T32, .BFI_MSB:
--- a/core/rexcode/arm32/encoder.odin
+++ b/core/rexcode/arm32/encoder.odin
@@ -267,7 +267,7 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op
 	     .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM,
 	     .IMM_COPROC, .IMM_COPROC_OP, .NEON_IMM, .IMM16_LO_HI:
 		return op.kind == .IMMEDIATE
-	case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL:
+	case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .REL_BF:
 		return op.kind == .RELATIVE
 	case .COND:
 		return op.kind == .IMMEDIATE
@@ -561,6 +561,30 @@ pack_operand_inline :: #force_inline proc(
 		})
 		return 0

+	// ---- ARMv8.1-M Branch Future -------------------------------------------
+	case .BF_BOFF:
+		append(relocs, Relocation{
+			offset = pc, label_id = u32(op.relative),
+			type = .BF_BOFF_T32, size = 4, inst_idx = inst_idx,
+		})
+		return 0
+	case .BF_BLOC:
+		append(relocs, Relocation{
+			offset = pc, label_id = u32(op.relative),
+			type = .BF_BLOC_T32, size = 4, inst_idx = inst_idx,
+		})
+		return 0
+	case .BF_BELSE:
+		append(relocs, Relocation{
+			offset = pc, label_id = u32(op.relative),
+			type = .BFCSEL_ELSE_T32, size = 4, inst_idx = inst_idx,
+		})
+		return 0
+	case .BF_RM:
+		return (u32(reg_hw(op.reg)) & 0xF) << 16   // Rm at hw0[3:0] (word bits 19:16)
+	case .BFCSEL_COND:
+		return (u32(op.immediate) & 0xF) << 18     // cond at hw0[5:2] (word bits 21:18)
+
 	// ---- Misc --------------------------------------------------------------
 	case .PSR_FIELD_MASK:   return encode_psr_field(u8(op.immediate))
 	case .SYSM_FIELD:       return u32(op.immediate) & 0xFF
@@ -727,6 +751,31 @@ resolve_relocation_inline :: #force_inline proc(
 		write_u16_le(code, r.offset + 2, existing | (imm11 << 1))
 		return true

+	case .BF_BOFF_T32:
+		// Branch Future bf-point: imm4 = (label-(PC+4))/2 at hw0[10:7].
+		rel := i32(target) - (i32(r.offset) + 4) + r.addend
+		if rel & 1 != 0 || rel < 0 || rel >= (1 << 5) {
+			append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE})
+			return true
+		}
+		imm4 := u16(u32(rel >> 1) & 0xF)
+		hw0  := read_u16_le(code, r.offset)
+		write_u16_le(code, r.offset, hw0 | (imm4 << 7))
+		return true
+
+	case .BF_BLOC_T32:
+		// Branch Future target: val=(label-(PC+4))/2; J at hw1[11], imm10 at hw1[10:1].
+		rel := i32(target) - (i32(r.offset) + 4) + r.addend
+		if rel & 1 != 0 || rel < -(1 << 11) || rel >= (1 << 11) {
+			append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE})
+			return true
+		}
+		val   := u32(rel >> 1)
+		hw1   := read_u16_le(code, r.offset + 2)
+		hw1 |= u16((val & 1) << 11) | u16(((val >> 1) & 0x3FF) << 1)
+		write_u16_le(code, r.offset + 2, hw1)
+		return true
+
 	case .LDR_LITERAL_A32:
 		rel := i32(target) - (i32(r.offset) + 8) + r.addend
 		u_bit: u32 = rel >= 0 ? 1 : 0
--- a/core/rexcode/arm32/encoding_types.odin
+++ b/core/rexcode/arm32/encoding_types.odin
@@ -214,6 +214,7 @@ Operand_Type :: enum u8 {
 	REL11,                // T16 B<cond>
 	REL8,                 // T16 conditional branch (signed 8-bit)
 	REL_LDR_LITERAL,      // PC-relative literal load offset
+	REL_BF,               // ARMv8.1-M Branch Future label (bf-point / branch target)

 	// ---- Condition code ----
 	COND,                 // 4-bit cond field (for IT block / B<cond> / etc.)
@@ -352,6 +353,12 @@ Operand_Encoding :: enum u8 {
 	BRANCH_11_T16,         // T16 unconditional (imm11, scaled ×2, ±2KB)
 	BRANCH_8_T16,          // T16 conditional (cond + imm8, scaled ×2, ±256B)
 	BRANCH_CBZ,            // T16 CBZ/CBNZ (i + imm5 + Rn, scaled ×2)
+	// ARMv8.1-M Branch Future fields (T32):
+	BF_BOFF,               // bf-point offset: imm4 at hw0[10:7], (label-PC-4)/2
+	BF_BLOC,               // branch target: J at hw1[11] + imm10 at hw1[10:1]
+	BF_BELSE,              // BFCSEL else-target: imm4 at hw0[? ] (relative to bf-point)
+	BF_RM,                 // BFLX/BFX register target at hw0[3:0]
+	BFCSEL_COND,           // BFCSEL condition at hw0[5:2]

 	// ---- Misc ----
 	PSR_FIELD_MASK,        // APSR fields_mask at bits 19-16 (MSR)
--- a/core/rexcode/arm32/mnemonic_builders.odin
+++ b/core/rexcode/arm32/mnemonic_builders.odin
@@ -1174,6 +1174,14 @@ inst_letp_rel                    :: #force_inline proc "contextless" (offset: i6
 emit_letp_rel                    :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) }
 inst_lctp_none                   :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
 emit_lctp_none                   :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) }
+inst_bf_rel_rel                  :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BF, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} }
+emit_bf_rel_rel                  :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bf_rel_rel(offset, offset2)) }
+inst_bfi_br_rel_r                :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFI_BR, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} }
+emit_bfi_br_rel_r                :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bfi_br_rel_r(offset, src)) }
+inst_bfl_rel_rel                 :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BFL, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} }
+emit_bfl_rel_rel                 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bfl_rel_rel(offset, offset2)) }
+inst_bflx_rel_r                  :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFLX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} }
+emit_bflx_rel_r                  :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bflx_rel_r(offset, src)) }
 inst_cx1_cp_r_imm                :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
 emit_cx1_cp_r_imm                :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) }
 inst_cx1a_cp_r_imm               :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
@@ -2431,6 +2439,14 @@ inst_letp                             :: inst_letp_rel
 emit_letp                             :: emit_letp_rel
 inst_lctp                             :: inst_lctp_none
 emit_lctp                             :: emit_lctp_none
+inst_bf                               :: inst_bf_rel_rel
+emit_bf                               :: emit_bf_rel_rel
+inst_bfi_br                           :: inst_bfi_br_rel_r
+emit_bfi_br                           :: emit_bfi_br_rel_r
+inst_bfl                              :: inst_bfl_rel_rel
+emit_bfl                              :: emit_bfl_rel_rel
+inst_bflx                             :: inst_bflx_rel_r
+emit_bflx                             :: emit_bflx_rel_r
 inst_cx1                              :: inst_cx1_cp_r_imm
 emit_cx1                              :: emit_cx1_cp_r_imm
 inst_cx1a                             :: inst_cx1a_cp_r_imm
--- a/core/rexcode/arm32/reloc.odin
+++ b/core/rexcode/arm32/reloc.odin
@@ -41,6 +41,11 @@ Relocation_Type :: enum u8 {
 	BRANCH_T32_WLS,        // WLS / WLSTP imm11
 	BRANCH_T32_LE,         // LE / LETP imm11

+	// T32 Branch Future (ARMv8.1-M)
+	BF_BOFF_T32,           // bf-point: imm4 at hw0[10:7] = (label - (PC+4))/2
+	BF_BLOC_T32,           // branch target: J at hw1[11] + imm10 at hw1[10:1]
+	BFCSEL_ELSE_T32,       // BFCSEL else-target relative to the bf-point
+
 	// Literal load (ADR / LDR PC-rel)
 	LDR_LITERAL_A32,       // signed 12-bit (U bit + imm12)
 	LDR_LITERAL_T32,       // signed 12-bit (U bit + imm12) Thumb-2
--- a/core/rexcode/arm32/tablegen/encoding_table.odin
+++ b/core/rexcode/arm32/tablegen/encoding_table.odin
@@ -3103,13 +3103,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
 	},
 	.WLSTP = {
 		// WLSTP.<size>: bits 22:20 carry size selector (B/H/W/D)
-		{.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
+		{.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
 	},
 	.DLS = {
 		{.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}},
 	},
 	.DLSTP = {
-		{.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}},
+		{.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}},
 	},
 	.LE = {
 		{.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
@@ -3121,10 +3121,22 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
 		{.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}},
 	},

-	// BF / BFL / BFLX / BFCSEL / BFI_BR (branch future, ARMv8.1-M).
-	// These encodings are scattered/relative and are intentionally left as
-	// placeholders pending dedicated LLVM-verified bit-pattern work. The
-	// mnemonics remain in the enum so callers can refer to them.
+	// BF / BFL / BFLX / BFI_BR (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1.
+	// bf-point: imm4 = (label-(PC+4))/2 at hw0[10:7]; branch target: val =
+	// (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target
+	// is a register Rm at hw0[3:0]. (BFCSEL has an extra else-target + condition.)
+	.BF = {
+		{.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
+	},
+	.BFL = {
+		{.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
+	},
+	.BFLX = {
+		{.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
+	},
+	.BFI_BR = {
+		{.BFI_BR, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}},
+	},

 	// =========================================================================
 	// Custom Datapath Extension (CDE) -- Cortex-M33+
--- a/core/rexcode/arm32/tablegen/generated/decode_tables.odin
+++ b/core/rexcode/arm32/tablegen/generated/decode_tables.odin
--- a/core/rexcode/arm32/tablegen/generated/encode_tables.odin
+++ b/core/rexcode/arm32/tablegen/generated/encode_tables.odin
@@ -8,7 +8,7 @@ package rexcode_arm32_generated
 import lib "../.."

@(rodata)
-ENCODE_FORMS := [1675]lib.Encoding{
+ENCODE_FORMS := [1679]lib.Encoding{
 	// .AND
 	{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} },
 	{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} },
@@ -2031,17 +2031,25 @@ ENCODE_FORMS := [1675]lib.Encoding{
 	// .WLS
 	{ .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true} },
 	// .WLSTP
-	{ .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {branch=true, thumb32=true} },
+	{ .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true} },
 	// .DLS
 	{ .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} },
 	// .DLSTP
-	{ .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true} },
+	{ .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} },
 	// .LE
 	{ .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} },
 	// .LETP
 	{ .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} },
 	// .LCTP
 	{ .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} },
+	// .BF
+	{ .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} },
+	// .BFI_BR
+	{ .BFI_BR, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} },
+	// .BFL
+	{ .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} },
+	// .BFLX
+	{ .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} },
 	// .CX1
 	{ .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true} },
 	// .CX1A
@@ -2809,141 +2817,141 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
 	.LE            = { 1535,   1},
 	.LETP          = { 1536,   1},
 	.LCTP          = { 1537,   1},
-	.BF            = { 1538,   0},
-	.BFI_BR        = { 1538,   0},
-	.BFL           = { 1538,   0},
-	.BFLX          = { 1538,   0},
-	.BFCSEL        = { 1538,   0},
-	.CX1           = { 1538,   1},
-	.CX1A          = { 1539,   1},
-	.CX1D          = { 1540,   1},
-	.CX1DA         = { 1541,   1},
-	.CX2           = { 1542,   1},
-	.CX2A          = { 1543,   1},
-	.CX2D          = { 1544,   1},
-	.CX2DA         = { 1545,   1},
-	.CX3           = { 1546,   1},
-	.CX3A          = { 1547,   1},
-	.CX3D          = { 1548,   1},
-	.CX3DA         = { 1549,   1},
-	.VCX1          = { 1550,   2},
-	.VCX1A         = { 1552,   2},
-	.VCX2          = { 1554,   2},
-	.VCX2A         = { 1556,   2},
-	.VCX3          = { 1558,   2},
-	.VCX3A         = { 1560,   2},
-	.VPT           = { 1562,   1},
-	.VPST          = { 1563,   1},
-	.VPSEL         = { 1564,   1},
-	.VPNOT         = { 1565,   1},
-	.VCTP          = { 1566,   1},
-	.VADDV         = { 1567,   1},
-	.VADDVA        = { 1568,   1},
-	.VADDLV        = { 1569,   1},
-	.VADDLVA       = { 1570,   1},
-	.VMAXV         = { 1571,   1},
-	.VMAXAV        = { 1572,   1},
-	.VMINV         = { 1573,   1},
-	.VMINAV        = { 1574,   1},
-	.VMAXNMV       = { 1575,   1},
-	.VMAXNMAV      = { 1576,   1},
-	.VMINNMV       = { 1577,   1},
-	.VMINNMAV      = { 1578,   1},
-	.VABAV         = { 1579,   1},
-	.VMLADAV       = { 1580,   1},
-	.VMLADAVA      = { 1581,   1},
-	.VMLADAVX      = { 1582,   1},
-	.VMLADAVAX     = { 1583,   1},
-	.VMLALDAV      = { 1584,   1},
-	.VMLALDAVA     = { 1585,   1},
-	.VMLALDAVX     = { 1586,   1},
-	.VMLALDAVAX    = { 1587,   1},
-	.VMLSDAV       = { 1588,   1},
-	.VMLSDAVA      = { 1589,   1},
-	.VMLSDAVX      = { 1590,   1},
-	.VMLSDAVAX     = { 1591,   1},
-	.VMLSLDAV      = { 1592,   1},
-	.VMLSLDAVA     = { 1593,   1},
-	.VMLSLDAVX     = { 1594,   1},
-	.VMLSLDAVAX    = { 1595,   1},
-	.VRMLALDAVH    = { 1596,   1},
-	.VRMLALDAVHA   = { 1597,   1},
-	.VRMLALDAVHX   = { 1598,   1},
-	.VRMLALDAVHAX  = { 1599,   1},
-	.VRMLSLDAVH    = { 1600,   1},
-	.VRMLSLDAVHA   = { 1601,   1},
-	.VRMLSLDAVHX   = { 1602,   1},
-	.VRMLSLDAVHAX  = { 1603,   1},
-	.VMLAV         = { 1604,   1},
-	.VMLAVA        = { 1605,   1},
-	.VMLSV         = { 1606,   1},
-	.VMLSVA        = { 1607,   1},
-	.VCMUL         = { 1608,   1},
-	.VHCADD        = { 1609,   1},
-	.VBRSR         = { 1610,   1},
-	.VSHLC         = { 1611,   1},
-	.VDDUP         = { 1612,   1},
-	.VIDUP         = { 1613,   1},
-	.VDWDUP        = { 1614,   1},
-	.VIWDUP        = { 1615,   1},
-	.VMOVNB        = { 1616,   1},
-	.VMOVNT        = { 1617,   1},
-	.VQMOVNB       = { 1618,   1},
-	.VQMOVNT       = { 1619,   1},
-	.VQMOVUNB      = { 1620,   1},
-	.VQMOVUNT      = { 1621,   1},
-	.VSHLLB        = { 1622,   1},
-	.VSHLLT        = { 1623,   1},
-	.VMULLB        = { 1624,   1},
-	.VMULLT        = { 1625,   1},
-	.VMLALB        = { 1626,   1},
-	.VMLALT        = { 1627,   1},
-	.VMLSLB        = { 1628,   1},
-	.VMLSLT        = { 1629,   1},
-	.VSHRNB        = { 1630,   1},
-	.VSHRNT        = { 1631,   1},
-	.VRSHRNB       = { 1632,   1},
-	.VRSHRNT       = { 1633,   1},
-	.VQSHRNB       = { 1634,   1},
-	.VQSHRNT       = { 1635,   1},
-	.VQRSHRNB      = { 1636,   1},
-	.VQRSHRNT      = { 1637,   1},
-	.VQSHRUNB      = { 1638,   1},
-	.VQSHRUNT      = { 1639,   1},
-	.VQRSHRUNB     = { 1640,   1},
-	.VQRSHRUNT     = { 1641,   1},
-	.VMOV_Q_R      = { 1642,   1},
-	.VMOV_R_Q      = { 1643,   1},
-	.VMOV_2GPR_Q   = { 1644,   1},
-	.VQDMLADH      = { 1645,   1},
-	.VQDMLADHX     = { 1646,   1},
-	.VQDMLSDH      = { 1647,   1},
-	.VQDMLSDHX     = { 1648,   1},
-	.VQRDMLADH     = { 1649,   1},
-	.VQRDMLADHX    = { 1650,   1},
-	.VQRDMLSDH     = { 1651,   1},
-	.VQRDMLSDHX    = { 1652,   1},
-	.VHCADD_SAT    = { 1653,   1},
-	.VCMLA_MVE     = { 1654,   1},
-	.VLDRB         = { 1655,   1},
-	.VLDRH         = { 1656,   1},
-	.VLDRW         = { 1657,   1},
-	.VLDRD         = { 1658,   1},
-	.VSTRB         = { 1659,   1},
-	.VSTRH         = { 1660,   1},
-	.VSTRW         = { 1661,   1},
-	.VSTRD         = { 1662,   1},
-	.VLD20         = { 1663,   1},
-	.VLD21         = { 1664,   1},
-	.VLD40         = { 1665,   1},
-	.VLD41         = { 1666,   1},
-	.VLD42         = { 1667,   1},
-	.VLD43         = { 1668,   1},
-	.VST20         = { 1669,   1},
-	.VST21         = { 1670,   1},
-	.VST40         = { 1671,   1},
-	.VST41         = { 1672,   1},
-	.VST42         = { 1673,   1},
-	.VST43         = { 1674,   1},
-	._COUNT        = { 1675,   0},
+	.BF            = { 1538,   1},
+	.BFI_BR        = { 1539,   1},
+	.BFL           = { 1540,   1},
+	.BFLX          = { 1541,   1},
+	.BFCSEL        = { 1542,   0},
+	.CX1           = { 1542,   1},
+	.CX1A          = { 1543,   1},
+	.CX1D          = { 1544,   1},
+	.CX1DA         = { 1545,   1},
+	.CX2           = { 1546,   1},
+	.CX2A          = { 1547,   1},
+	.CX2D          = { 1548,   1},
+	.CX2DA         = { 1549,   1},
+	.CX3           = { 1550,   1},
+	.CX3A          = { 1551,   1},
+	.CX3D          = { 1552,   1},
+	.CX3DA         = { 1553,   1},
+	.VCX1          = { 1554,   2},
+	.VCX1A         = { 1556,   2},
+	.VCX2          = { 1558,   2},
+	.VCX2A         = { 1560,   2},
+	.VCX3          = { 1562,   2},
+	.VCX3A         = { 1564,   2},
+	.VPT           = { 1566,   1},
+	.VPST          = { 1567,   1},
+	.VPSEL         = { 1568,   1},
+	.VPNOT         = { 1569,   1},
+	.VCTP          = { 1570,   1},
+	.VADDV         = { 1571,   1},
+	.VADDVA        = { 1572,   1},
+	.VADDLV        = { 1573,   1},
+	.VADDLVA       = { 1574,   1},
+	.VMAXV         = { 1575,   1},
+	.VMAXAV        = { 1576,   1},
+	.VMINV         = { 1577,   1},
+	.VMINAV        = { 1578,   1},
+	.VMAXNMV       = { 1579,   1},
+	.VMAXNMAV      = { 1580,   1},
+	.VMINNMV       = { 1581,   1},
+	.VMINNMAV      = { 1582,   1},
+	.VABAV         = { 1583,   1},
+	.VMLADAV       = { 1584,   1},
+	.VMLADAVA      = { 1585,   1},
+	.VMLADAVX      = { 1586,   1},
+	.VMLADAVAX     = { 1587,   1},
+	.VMLALDAV      = { 1588,   1},
+	.VMLALDAVA     = { 1589,   1},
+	.VMLALDAVX     = { 1590,   1},
+	.VMLALDAVAX    = { 1591,   1},
+	.VMLSDAV       = { 1592,   1},
+	.VMLSDAVA      = { 1593,   1},
+	.VMLSDAVX      = { 1594,   1},
+	.VMLSDAVAX     = { 1595,   1},
+	.VMLSLDAV      = { 1596,   1},
+	.VMLSLDAVA     = { 1597,   1},
+	.VMLSLDAVX     = { 1598,   1},
+	.VMLSLDAVAX    = { 1599,   1},
+	.VRMLALDAVH    = { 1600,   1},
+	.VRMLALDAVHA   = { 1601,   1},
+	.VRMLALDAVHX   = { 1602,   1},
+	.VRMLALDAVHAX  = { 1603,   1},
+	.VRMLSLDAVH    = { 1604,   1},
+	.VRMLSLDAVHA   = { 1605,   1},
+	.VRMLSLDAVHX   = { 1606,   1},
+	.VRMLSLDAVHAX  = { 1607,   1},
+	.VMLAV         = { 1608,   1},
+	.VMLAVA        = { 1609,   1},
+	.VMLSV         = { 1610,   1},
+	.VMLSVA        = { 1611,   1},
+	.VCMUL         = { 1612,   1},
+	.VHCADD        = { 1613,   1},
+	.VBRSR         = { 1614,   1},
+	.VSHLC         = { 1615,   1},
+	.VDDUP         = { 1616,   1},
+	.VIDUP         = { 1617,   1},
+	.VDWDUP        = { 1618,   1},
+	.VIWDUP        = { 1619,   1},
+	.VMOVNB        = { 1620,   1},
+	.VMOVNT        = { 1621,   1},
+	.VQMOVNB       = { 1622,   1},
+	.VQMOVNT       = { 1623,   1},
+	.VQMOVUNB      = { 1624,   1},
+	.VQMOVUNT      = { 1625,   1},
+	.VSHLLB        = { 1626,   1},
+	.VSHLLT        = { 1627,   1},
+	.VMULLB        = { 1628,   1},
+	.VMULLT        = { 1629,   1},
+	.VMLALB        = { 1630,   1},
+	.VMLALT        = { 1631,   1},
+	.VMLSLB        = { 1632,   1},
+	.VMLSLT        = { 1633,   1},
+	.VSHRNB        = { 1634,   1},
+	.VSHRNT        = { 1635,   1},
+	.VRSHRNB       = { 1636,   1},
+	.VRSHRNT       = { 1637,   1},
+	.VQSHRNB       = { 1638,   1},
+	.VQSHRNT       = { 1639,   1},
+	.VQRSHRNB      = { 1640,   1},
+	.VQRSHRNT      = { 1641,   1},
+	.VQSHRUNB      = { 1642,   1},
+	.VQSHRUNT      = { 1643,   1},
+	.VQRSHRUNB     = { 1644,   1},
+	.VQRSHRUNT     = { 1645,   1},
+	.VMOV_Q_R      = { 1646,   1},
+	.VMOV_R_Q      = { 1647,   1},
+	.VMOV_2GPR_Q   = { 1648,   1},
+	.VQDMLADH      = { 1649,   1},
+	.VQDMLADHX     = { 1650,   1},
+	.VQDMLSDH      = { 1651,   1},
+	.VQDMLSDHX     = { 1652,   1},
+	.VQRDMLADH     = { 1653,   1},
+	.VQRDMLADHX    = { 1654,   1},
+	.VQRDMLSDH     = { 1655,   1},
+	.VQRDMLSDHX    = { 1656,   1},
+	.VHCADD_SAT    = { 1657,   1},
+	.VCMLA_MVE     = { 1658,   1},
+	.VLDRB         = { 1659,   1},
+	.VLDRH         = { 1660,   1},
+	.VLDRW         = { 1661,   1},
+	.VLDRD         = { 1662,   1},
+	.VSTRB         = { 1663,   1},
+	.VSTRH         = { 1664,   1},
+	.VSTRW         = { 1665,   1},
+	.VSTRD         = { 1666,   1},
+	.VLD20         = { 1667,   1},
+	.VLD21         = { 1668,   1},
+	.VLD40         = { 1669,   1},
+	.VLD41         = { 1670,   1},
+	.VLD42         = { 1671,   1},
+	.VLD43         = { 1672,   1},
+	.VST20         = { 1673,   1},
+	.VST21         = { 1674,   1},
+	.VST40         = { 1675,   1},
+	.VST41         = { 1676,   1},
+	.VST42         = { 1677,   1},
+	.VST43         = { 1678,   1},
+	._COUNT        = { 1679,   0},
 }
--- a/core/rexcode/arm32/tables/arm32.bucket_list.bin
+++ b/core/rexcode/arm32/tables/arm32.bucket_list.bin
--- a/core/rexcode/arm32/tables/arm32.encode_forms.bin
+++ b/core/rexcode/arm32/tables/arm32.encode_forms.bin
--- a/core/rexcode/arm32/tables/arm32.encode_runs.bin
+++ b/core/rexcode/arm32/tables/arm32.encode_runs.bin
--- a/core/rexcode/arm32/tables/arm32.entries.bin
+++ b/core/rexcode/arm32/tables/arm32.entries.bin
--- a/core/rexcode/arm32/tables/arm32.form_idx.bin
+++ b/core/rexcode/arm32/tables/arm32.form_idx.bin
--- a/core/rexcode/arm32/tables/arm32.idx_t16.bin
+++ b/core/rexcode/arm32/tables/arm32.idx_t16.bin
--- a/core/rexcode/arm32/tables/arm32.idx_t32.bin
+++ b/core/rexcode/arm32/tables/arm32.idx_t32.bin
--- a/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin
+++ b/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin
--- a/core/rexcode/arm32/tools/gen_mnemonic_builders.odin
+++ b/core/rexcode/arm32/tools/gen_mnemonic_builders.odin
@@ -119,7 +119,7 @@ operand_class :: proc(ot: a.Operand_Type) -> Operand_Class {
 		return .MEM

 	// ---- PC-relative branch targets & low-overhead-loop targets ----
-	case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .MVE_LOOP_TGT:
+	case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .MVE_LOOP_TGT, .REL_BF:
 		return .REL

 	// ---- Plain registers (single Register value) ----
@@ -187,6 +187,7 @@ operand_suffix :: proc(ot: a.Operand_Type) -> string {
 	case .REL11:         return "rel"
 	case .REL8:          return "rel"
 	case .REL_LDR_LITERAL: return "rel"
+	case .REL_BF:        return "rel"
 	case .COPROC_REG:    return "crd"
 	case .COPROC_NUM:    return "cpn"
 	case .PSR_FIELD:     return "psr"