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rexcode/arm64: SVE predicated/compare/predicate-logical/SVE2 encode forms (37)
Predicated FP round (FRINTN/P/M/Z/A/X/I, FRECPX), reversed predicated shifts (ASRR/LSLR/LSRR) and FP (FSUBR/FDIVR), FP compare (FCMEQ/GE/GT/ NE/UO + vs-zero FCMLE/FCMLT), integer compare aliases (CMPLE/LO/LS/LT), predicate logical (NANDS/NORS/ORNS), predicate break (BRKPA/BRKPB, BRKA/BRKB + flag-setting BRKAS/BRKBS), SVE2 EOR3/BCAX, INSR, COMPACT. New specgen SVE section: a generic emitter assembles each form all-zero then one variant per field at its max (Z 31, 3-bit Pg 7, 4-bit Pd/Pg/Pn/ Pm 15, GPR wzr/xzr) and derives mask = ~union. Operand placements verified vs llvm-mc: the reversed/destructive ops put Zm at VN (5-9); the CMPLE/LO/LS/LT aliases swap operands (VM/VN); EOR3/BCAX place the 3rd src at VM and 4th at VN. All 22 representative forms byte-exact and decode-clean; 461 tests green. (BRKN + CPY/EXT/MOV/NOT_P/FFR/XAR stragglers next.)
This commit is contained in:
Brendan Punsky
@@ -1351,6 +1351,12 @@ inst_sve_lsl_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2
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emit_sve_lsl_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsl_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lsr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lsr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_asrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_asrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lslr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSLR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lslr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lslr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_lsrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
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emit_sve_lsrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_abs_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ABS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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emit_sve_abs_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_abs_pred_z_p_z(rz, rz2, rz3)) }
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inst_sve_neg_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NEG_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} }
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@@ -1377,10 +1383,14 @@ inst_sve_fadd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2
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emit_sve_fadd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fadd_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fsub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fsub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsub_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fsubr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUBR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fsubr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsubr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmul_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIV_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fdivr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIVR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fdivr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdivr_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAX_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmax_pred_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMIN_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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@@ -1395,6 +1405,22 @@ inst_sve_fneg_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2
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emit_sve_fneg_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fneg_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_fsqrt_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSQRT_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_fsqrt_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsqrt_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_frecpx_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPX_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frecpx_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecpx_z_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintn_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintp_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintm_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintz_z_p_z(rz, rz2, rz3)) }
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inst_sve_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinta_z_p_z(rz, rz2, rz3)) }
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inst_sve_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintx_z_p_z(rz, rz2, rz3)) }
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inst_sve_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
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emit_sve_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinti_z_p_z(rz, rz2, rz3)) }
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inst_sve_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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emit_sve_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmla_z_p_z_z(rz, rz2, rz3, rz4)) }
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inst_sve_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
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@@ -1427,6 +1453,12 @@ inst_sve_orrs_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2
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emit_sve_orrs_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orrs_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_eors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_eors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eors_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nands_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_nors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_nors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nors_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_orns_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORNS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
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emit_sve_orns_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orns_p_p_p_p_p(rz, rz2, rz3, rz4)) }
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inst_sve_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} }
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emit_sve_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrue_p_i(rz, imm)) }
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inst_sve_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} }
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@@ -1437,6 +1469,18 @@ inst_sve_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2
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emit_sve_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pfirst_p_p_p(rz, rz2, rz3)) }
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inst_sve_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pnext_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brka_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkb_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkas_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkbs_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
|
||||
emit_sve_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} }
|
||||
emit_sve_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
@@ -1445,12 +1489,36 @@ inst_sve_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2
|
||||
emit_sve_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmple_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
|
||||
emit_sve_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
|
||||
emit_sve_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
|
||||
emit_sve_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
|
||||
emit_sve_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
|
||||
emit_sve_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmle_p_p_z(rz, rz2, rz3)) }
|
||||
inst_sve_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} }
|
||||
emit_sve_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmlt_p_p_z(rz, rz2, rz3)) }
|
||||
inst_sve_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} }
|
||||
emit_sve_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_dup_z_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_DUP_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} }
|
||||
emit_sve_dup_z_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_dup_z_z_r(rz, src)) }
|
||||
inst_sve_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} }
|
||||
emit_sve_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_insr_z_r(rz, src)) }
|
||||
inst_sve_rev_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} }
|
||||
emit_sve_rev_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_z_z_z(rz, rz2)) }
|
||||
inst_sve_rev_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} }
|
||||
@@ -1481,6 +1549,8 @@ inst_sve_trn1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2
|
||||
emit_sve_trn1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_p_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_trn2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} }
|
||||
emit_sve_trn2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_p_p_p_p(rz, rz2, rz3)) }
|
||||
inst_sve_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} }
|
||||
emit_sve_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_compact_z_p_z(rz, rz2, rz3)) }
|
||||
inst_sve_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
|
||||
emit_sve_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_z_p_m(rz, rz2, mem)) }
|
||||
inst_sve_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} }
|
||||
@@ -1559,6 +1629,10 @@ inst_sve_aesmc_z :: #force_inline proc "contextless" (rz: u8) ->
|
||||
emit_sve_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesmc_z(rz)) }
|
||||
inst_sve_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} }
|
||||
emit_sve_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesimc_z(rz)) }
|
||||
inst_sve_bcax_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BCAX_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
|
||||
emit_sve_bcax_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bcax_z_z_z_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_eor3_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR3_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} }
|
||||
emit_sve_eor3_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor3_z_z_z_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
emit_sve_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_match_p_p_z_z(rz, rz2, rz3, rz4)) }
|
||||
inst_sve_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} }
|
||||
@@ -3422,6 +3496,12 @@ inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z
|
||||
emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z
|
||||
inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z
|
||||
emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z
|
||||
inst_sve_asrr_pred :: inst_sve_asrr_pred_z_p_z_z
|
||||
emit_sve_asrr_pred :: emit_sve_asrr_pred_z_p_z_z
|
||||
inst_sve_lslr_pred :: inst_sve_lslr_pred_z_p_z_z
|
||||
emit_sve_lslr_pred :: emit_sve_lslr_pred_z_p_z_z
|
||||
inst_sve_lsrr_pred :: inst_sve_lsrr_pred_z_p_z_z
|
||||
emit_sve_lsrr_pred :: emit_sve_lsrr_pred_z_p_z_z
|
||||
inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z
|
||||
emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z
|
||||
inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z
|
||||
@@ -3448,10 +3528,14 @@ inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z
|
||||
emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z
|
||||
inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z
|
||||
emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z
|
||||
inst_sve_fsubr_pred :: inst_sve_fsubr_pred_z_p_z_z
|
||||
emit_sve_fsubr_pred :: emit_sve_fsubr_pred_z_p_z_z
|
||||
inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z
|
||||
emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z
|
||||
inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z
|
||||
emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z
|
||||
inst_sve_fdivr_pred :: inst_sve_fdivr_pred_z_p_z_z
|
||||
emit_sve_fdivr_pred :: emit_sve_fdivr_pred_z_p_z_z
|
||||
inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z
|
||||
emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z
|
||||
inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z
|
||||
@@ -3466,6 +3550,22 @@ inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z
|
||||
emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z
|
||||
inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z
|
||||
emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z
|
||||
inst_sve_frecpx_z :: inst_sve_frecpx_z_z_p_z
|
||||
emit_sve_frecpx_z :: emit_sve_frecpx_z_z_p_z
|
||||
inst_sve_frintn :: inst_sve_frintn_z_p_z
|
||||
emit_sve_frintn :: emit_sve_frintn_z_p_z
|
||||
inst_sve_frintp :: inst_sve_frintp_z_p_z
|
||||
emit_sve_frintp :: emit_sve_frintp_z_p_z
|
||||
inst_sve_frintm :: inst_sve_frintm_z_p_z
|
||||
emit_sve_frintm :: emit_sve_frintm_z_p_z
|
||||
inst_sve_frintz :: inst_sve_frintz_z_p_z
|
||||
emit_sve_frintz :: emit_sve_frintz_z_p_z
|
||||
inst_sve_frinta :: inst_sve_frinta_z_p_z
|
||||
emit_sve_frinta :: emit_sve_frinta_z_p_z
|
||||
inst_sve_frintx :: inst_sve_frintx_z_p_z
|
||||
emit_sve_frintx :: emit_sve_frintx_z_p_z
|
||||
inst_sve_frinti :: inst_sve_frinti_z_p_z
|
||||
emit_sve_frinti :: emit_sve_frinti_z_p_z
|
||||
inst_sve_fmla :: inst_sve_fmla_z_p_z_z
|
||||
emit_sve_fmla :: emit_sve_fmla_z_p_z_z
|
||||
inst_sve_fmls :: inst_sve_fmls_z_p_z_z
|
||||
@@ -3498,6 +3598,12 @@ inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p
|
||||
emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p
|
||||
inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p
|
||||
emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p
|
||||
inst_sve_nands_p :: inst_sve_nands_p_p_p_p_p
|
||||
emit_sve_nands_p :: emit_sve_nands_p_p_p_p_p
|
||||
inst_sve_nors_p :: inst_sve_nors_p_p_p_p_p
|
||||
emit_sve_nors_p :: emit_sve_nors_p_p_p_p_p
|
||||
inst_sve_orns_p :: inst_sve_orns_p_p_p_p_p
|
||||
emit_sve_orns_p :: emit_sve_orns_p_p_p_p_p
|
||||
inst_sve_ptrue :: inst_sve_ptrue_p_i
|
||||
emit_sve_ptrue :: emit_sve_ptrue_p_i
|
||||
inst_sve_ptrues :: inst_sve_ptrues_p_i
|
||||
@@ -3508,6 +3614,18 @@ inst_sve_pfirst :: inst_sve_pfirst_p_p_p
|
||||
emit_sve_pfirst :: emit_sve_pfirst_p_p_p
|
||||
inst_sve_pnext :: inst_sve_pnext_p_p_p
|
||||
emit_sve_pnext :: emit_sve_pnext_p_p_p
|
||||
inst_sve_brka :: inst_sve_brka_p_p_p
|
||||
emit_sve_brka :: emit_sve_brka_p_p_p
|
||||
inst_sve_brkb :: inst_sve_brkb_p_p_p
|
||||
emit_sve_brkb :: emit_sve_brkb_p_p_p
|
||||
inst_sve_brkas :: inst_sve_brkas_p_p_p
|
||||
emit_sve_brkas :: emit_sve_brkas_p_p_p
|
||||
inst_sve_brkbs :: inst_sve_brkbs_p_p_p
|
||||
emit_sve_brkbs :: emit_sve_brkbs_p_p_p
|
||||
inst_sve_brkpa :: inst_sve_brkpa_p_p_p_p
|
||||
emit_sve_brkpa :: emit_sve_brkpa_p_p_p_p
|
||||
inst_sve_brkpb :: inst_sve_brkpb_p_p_p_p
|
||||
emit_sve_brkpb :: emit_sve_brkpb_p_p_p_p
|
||||
inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z
|
||||
emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z
|
||||
inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z
|
||||
@@ -3516,12 +3634,36 @@ inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z
|
||||
emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z
|
||||
inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z
|
||||
emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z
|
||||
inst_sve_cmple :: inst_sve_cmple_p_p_z_z
|
||||
emit_sve_cmple :: emit_sve_cmple_p_p_z_z
|
||||
inst_sve_cmplt :: inst_sve_cmplt_p_p_z_z
|
||||
emit_sve_cmplt :: emit_sve_cmplt_p_p_z_z
|
||||
inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z
|
||||
emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z
|
||||
inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z
|
||||
emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z
|
||||
inst_sve_cmplo :: inst_sve_cmplo_p_p_z_z
|
||||
emit_sve_cmplo :: emit_sve_cmplo_p_p_z_z
|
||||
inst_sve_cmpls :: inst_sve_cmpls_p_p_z_z
|
||||
emit_sve_cmpls :: emit_sve_cmpls_p_p_z_z
|
||||
inst_sve_fcmeq :: inst_sve_fcmeq_p_p_z_z
|
||||
emit_sve_fcmeq :: emit_sve_fcmeq_p_p_z_z
|
||||
inst_sve_fcmne :: inst_sve_fcmne_p_p_z_z
|
||||
emit_sve_fcmne :: emit_sve_fcmne_p_p_z_z
|
||||
inst_sve_fcmge :: inst_sve_fcmge_p_p_z_z
|
||||
emit_sve_fcmge :: emit_sve_fcmge_p_p_z_z
|
||||
inst_sve_fcmgt :: inst_sve_fcmgt_p_p_z_z
|
||||
emit_sve_fcmgt :: emit_sve_fcmgt_p_p_z_z
|
||||
inst_sve_fcmle :: inst_sve_fcmle_p_p_z
|
||||
emit_sve_fcmle :: emit_sve_fcmle_p_p_z
|
||||
inst_sve_fcmlt :: inst_sve_fcmlt_p_p_z
|
||||
emit_sve_fcmlt :: emit_sve_fcmlt_p_p_z
|
||||
inst_sve_fcmuo :: inst_sve_fcmuo_p_p_z_z
|
||||
emit_sve_fcmuo :: emit_sve_fcmuo_p_p_z_z
|
||||
inst_sve_dup_z :: inst_sve_dup_z_z_r
|
||||
emit_sve_dup_z :: emit_sve_dup_z_z_r
|
||||
inst_sve_insr :: inst_sve_insr_z_r
|
||||
emit_sve_insr :: emit_sve_insr_z_r
|
||||
inst_sve_rev_z :: inst_sve_rev_z_z_z
|
||||
emit_sve_rev_z :: emit_sve_rev_z_z_z
|
||||
inst_sve_rev_p :: inst_sve_rev_p_p_p
|
||||
@@ -3552,6 +3694,8 @@ inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p
|
||||
emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p
|
||||
inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p
|
||||
emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p
|
||||
inst_sve_compact :: inst_sve_compact_z_p_z
|
||||
emit_sve_compact :: emit_sve_compact_z_p_z
|
||||
inst_sve_ld1b :: inst_sve_ld1b_z_p_m
|
||||
emit_sve_ld1b :: emit_sve_ld1b_z_p_m
|
||||
inst_sve_ld1h :: inst_sve_ld1h_z_p_m
|
||||
@@ -3630,6 +3774,10 @@ inst_sve_aesmc :: inst_sve_aesmc_z
|
||||
emit_sve_aesmc :: emit_sve_aesmc_z
|
||||
inst_sve_aesimc :: inst_sve_aesimc_z
|
||||
emit_sve_aesimc :: emit_sve_aesimc_z
|
||||
inst_sve_bcax_z :: inst_sve_bcax_z_z_z_z_z
|
||||
emit_sve_bcax_z :: emit_sve_bcax_z_z_z_z_z
|
||||
inst_sve_eor3_z :: inst_sve_eor3_z_z_z_z_z
|
||||
emit_sve_eor3_z :: emit_sve_eor3_z_z_z_z_z
|
||||
inst_sve_match :: inst_sve_match_p_p_z_z
|
||||
emit_sve_match :: emit_sve_match_p_p_z_z
|
||||
inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z
|
||||
|
||||
@@ -4583,5 +4583,177 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}},
|
||||
{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}},
|
||||
},
|
||||
|
||||
// SVE predicated / compare / predicate-logical / SVE2.
|
||||
.SVE_FRINTN = {
|
||||
{.SVE_FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTP = {
|
||||
{.SVE_FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTM = {
|
||||
{.SVE_FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTZ = {
|
||||
{.SVE_FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTA = {
|
||||
{.SVE_FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTX = {
|
||||
{.SVE_FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRINTI = {
|
||||
{.SVE_FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FRECPX_Z = {
|
||||
{.SVE_FRECPX_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRECPX_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FRECPX_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_ASRR_PRED = {
|
||||
{.SVE_ASRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_ASRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_ASRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_ASRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_LSLR_PRED = {
|
||||
{.SVE_LSLR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSLR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSLR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSLR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_LSRR_PRED = {
|
||||
{.SVE_LSRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_LSRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FSUBR_PRED = {
|
||||
{.SVE_FSUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FSUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FSUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FDIVR_PRED = {
|
||||
{.SVE_FDIVR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FDIVR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_FDIVR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMEQ = {
|
||||
{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMGE = {
|
||||
{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMGT = {
|
||||
{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMNE = {
|
||||
{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMUO = {
|
||||
{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}},
|
||||
{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMLE = {
|
||||
{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}},
|
||||
{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}},
|
||||
{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_FCMLT = {
|
||||
{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}},
|
||||
{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}},
|
||||
{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_CMPLE = {
|
||||
{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}},
|
||||
},
|
||||
.SVE_CMPLO = {
|
||||
{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}},
|
||||
},
|
||||
.SVE_CMPLS = {
|
||||
{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}},
|
||||
},
|
||||
.SVE_CMPLT = {
|
||||
{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}},
|
||||
{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}},
|
||||
},
|
||||
.SVE_NANDS_P = {
|
||||
{.SVE_NANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}},
|
||||
},
|
||||
.SVE_NORS_P = {
|
||||
{.SVE_NORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}},
|
||||
},
|
||||
.SVE_ORNS_P = {
|
||||
{.SVE_ORNS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}},
|
||||
},
|
||||
.SVE_BRKPA = {
|
||||
{.SVE_BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}},
|
||||
},
|
||||
.SVE_BRKPB = {
|
||||
{.SVE_BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}},
|
||||
},
|
||||
.SVE_BRKA = {
|
||||
{.SVE_BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}},
|
||||
},
|
||||
.SVE_BRKB = {
|
||||
{.SVE_BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}},
|
||||
},
|
||||
.SVE_BRKAS = {
|
||||
{.SVE_BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}},
|
||||
},
|
||||
.SVE_BRKBS = {
|
||||
{.SVE_BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}},
|
||||
},
|
||||
.SVE_EOR3_Z = {
|
||||
{.SVE_EOR3_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_BCAX_Z = {
|
||||
{.SVE_BCAX_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_INSR = {
|
||||
{.SVE_INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}},
|
||||
{.SVE_INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}},
|
||||
{.SVE_INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}},
|
||||
{.SVE_INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}},
|
||||
},
|
||||
.SVE_COMPACT = {
|
||||
{.SVE_COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}},
|
||||
{.SVE_COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}},
|
||||
},
|
||||
// SPECGEN:END
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -538,6 +538,148 @@ do
|
||||
sections[#sections+1] = "\t// NEON modified immediate (MOVI/MVNI).\n" .. table.concat(blk, "\n")
|
||||
end
|
||||
|
||||
-- ---- SVE (predicated FP/round/compare, predicate logical/break, SVE2) -------
|
||||
-- These iterate element sizes; the predicate-destination forms select size via
|
||||
-- the Z-register operands. `bits`/`mask` come from llvm-mc: assemble all-zero,
|
||||
-- then one variant per field set to its max (Z reg 31, 3-bit Pg 7, 4-bit Pd/
|
||||
-- Pg/Pn/Pm 15, GPR 31 = wzr/xzr) and mask = ~union of the deltas.
|
||||
SVE_LLVM = "llvm-mc --assemble --arch=aarch64 --mattr=+sve,+sve2,+sve2-aes,+fullfp16 --show-encoding"
|
||||
local function sve_word(line)
|
||||
local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, SVE_LLVM))
|
||||
local out = p:read("*a"); p:close()
|
||||
local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)")
|
||||
if not b1 then return nil end
|
||||
return tonumber(b4..b3..b2..b1, 16)
|
||||
end
|
||||
do
|
||||
local blk = {}
|
||||
local E_HSD = {{"h","Z_REG_H",""},{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}}
|
||||
local E_BHSD = {{"b","Z_REG_B",""},{"h","Z_REG_H",""},{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}}
|
||||
local E_SD = {{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}}
|
||||
local function emit1(mnem, ops, enc, flags, fields, build)
|
||||
local zero = {}; for i=1,#fields do zero[i]=0 end
|
||||
local b0 = sve_word(build(zero)); if not b0 then skips[#skips+1]=mnem..":b0"; return nil end
|
||||
local vs = {}
|
||||
for i=1,#fields do
|
||||
local v={}; for j=1,#fields do v[j]=0 end; v[i]=fields[i]
|
||||
local w=sve_word(build(v)); if not w then skips[#skips+1]=mnem..":v"..i; return nil end; vs[#vs+1]=w
|
||||
end
|
||||
n_forms=n_forms+1
|
||||
return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .SVE, {%s}},",
|
||||
mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags)
|
||||
end
|
||||
local function block(mnem, rows)
|
||||
local r={}; for _,x in ipairs(rows) do if x then r[#r+1]=x end end
|
||||
if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(r,"\n")); n_mnem=n_mnem+1 end
|
||||
end
|
||||
local function g(v, x) if v==0 then return x and "x0" or "w0" else return x and "xzr" or "wzr" end end
|
||||
|
||||
-- predicated FP round: Zd.T, Pg/m, Zn.T (H/S/D)
|
||||
for _, it in ipairs({{"SVE_FRINTN","frintn"},{"SVE_FRINTP","frintp"},{"SVE_FRINTM","frintm"},
|
||||
{"SVE_FRINTZ","frintz"},{"SVE_FRINTA","frinta"},{"SVE_FRINTX","frintx"},{"SVE_FRINTI","frinti"},{"SVE_FRECPX_Z","frecpx"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_HSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .NONE}",e[2],e[2]),
|
||||
"{.VD, .PG, .VN, .NONE}", e[3], {31,7,31},
|
||||
function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s", it[2], v[1],t, v[2], v[3],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- reversed predicated shifts: Zd.T, Pg/m, Zd.T, Zm.T (B/H/S/D)
|
||||
for _, it in ipairs({{"SVE_ASRR_PRED","asrr"},{"SVE_LSLR_PRED","lslr"},{"SVE_LSRR_PRED","lsrr"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_BHSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .%s}",e[2],e[2],e[2]),
|
||||
"{.VD, .PG, .VD, .VN}", e[3], {31,7,31},
|
||||
function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[1],t, v[3],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- reversed predicated FP: Zd.T, Pg/m, Zd.T, Zm.T (H/S/D)
|
||||
for _, it in ipairs({{"SVE_FSUBR_PRED","fsubr"},{"SVE_FDIVR_PRED","fdivr"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_HSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .%s}",e[2],e[2],e[2]),
|
||||
"{.VD, .PG, .VD, .VN}", e[3], {31,7,31},
|
||||
function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[1],t, v[3],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- FP compare (reg) -> Pd.T: Pd.T, Pg/z, Zn.T, Zm.T (H/S/D)
|
||||
for _, it in ipairs({{"SVE_FCMEQ","fcmeq"},{"SVE_FCMGE","fcmge"},{"SVE_FCMGT","fcmgt"},{"SVE_FCMNE","fcmne"},{"SVE_FCMUO","fcmuo"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_HSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .%s}",e[2],e[2]),
|
||||
"{.PD, .PG, .VN, .VM}", e[3], {15,7,31,31},
|
||||
function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[3],t, v[4],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- FP compare vs zero -> Pd.T: Pd.T, Pg/z, Zn.T, #0.0 (H/S/D)
|
||||
for _, it in ipairs({{"SVE_FCMLE","fcmle"},{"SVE_FCMLT","fcmlt"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_HSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .NONE}",e[2]),
|
||||
"{.PD, .PG, .VN, .NONE}", e[3], {15,7,31},
|
||||
function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, #0.0", it[2], v[1],t, v[2], v[3],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- integer compare (reg) -> Pd.T: Pd.T, Pg/z, Zn.T, Zm.T (B/H/S/D)
|
||||
for _, it in ipairs({{"SVE_CMPLE","cmple"},{"SVE_CMPLO","cmplo"},{"SVE_CMPLS","cmpls"},{"SVE_CMPLT","cmplt"}}) do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_BHSD) do local t=e[1]
|
||||
rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .%s}",e[2],e[2]),
|
||||
"{.PD, .PG, .VM, .VN}", "sets_flags=true"..(e[3]~="" and ", "..e[3] or ""), {15,7,31,31},
|
||||
function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[3],t, v[4],t) end)
|
||||
end
|
||||
block(it[1], rows)
|
||||
end
|
||||
-- predicate logical (3-source) -> Pd.B: Pd.B, Pg/z, Pn.B, Pm.B
|
||||
for _, it in ipairs({{"SVE_NANDS_P","nands"},{"SVE_NORS_P","nors"},{"SVE_ORNS_P","orns"}}) do
|
||||
block(it[1], { emit1(it[1], "{.P_REG, .P_REG_ZERO, .P_REG, .P_REG}", "{.PD, .PG4, .PN, .PM}", "sets_flags=true", {15,15,15,15},
|
||||
function(v) return string.format("%s p%d.b, p%d/z, p%d.b, p%d.b", it[2], v[1], v[2], v[3], v[4]) end) })
|
||||
end
|
||||
-- predicate break (pair) -> Pd.B: Pd.B, Pg/z, Pn.B, Pm.B
|
||||
for _, it in ipairs({{"SVE_BRKPA","brkpa"},{"SVE_BRKPB","brkpb"},{"SVE_BRKN","brkn"}}) do
|
||||
block(it[1], { emit1(it[1], "{.P_REG, .P_REG_ZERO, .P_REG, .P_REG}", "{.PD, .PG4, .PN, .PM}", "", {15,15,15,15},
|
||||
function(v) return string.format("%s p%d.b, p%d/z, p%d.b, p%d.b", it[2], v[1], v[2], v[3], v[4]) end) })
|
||||
end
|
||||
-- predicate break (single) -> Pd.B: Pd.B, Pg/m, Pn.B (BRKA/BRKB merge; BRKAS/BRKBS /z+flags)
|
||||
for _, it in ipairs({{"SVE_BRKA","brka","/m",""},{"SVE_BRKB","brkb","/m",""},
|
||||
{"SVE_BRKAS","brkas","/z","sets_flags=true"},{"SVE_BRKBS","brkbs","/z","sets_flags=true"}}) do
|
||||
local pred = it[3]=="/m" and ".P_REG_MERGE" or ".P_REG_ZERO"
|
||||
block(it[1], { emit1(it[1], "{.P_REG, "..pred..", .P_REG, .NONE}", "{.PD, .PG4, .PN, .NONE}", it[4], {15,15,15},
|
||||
function(v) return string.format("%s p%d.b, p%d%s, p%d.b", it[2], v[1], v[2], it[3], v[3]) end) })
|
||||
end
|
||||
-- SVE2 crypto three-source (.D): Zd.D, Zd.D, Zn.D, Zm.D
|
||||
for _, it in ipairs({{"SVE_EOR3_Z","eor3"},{"SVE_BCAX_Z","bcax"}}) do
|
||||
block(it[1], { emit1(it[1], "{.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}", "{.VD, .VD, .VM, .VN}", "is_64=true", {31,31,31},
|
||||
function(v) return string.format("%s z%d.d, z%d.d, z%d.d, z%d.d", it[2], v[1], v[1], v[2], v[3]) end) })
|
||||
end
|
||||
-- INSR: Zd.T, Wn/Xn (X for .D)
|
||||
do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_BHSD) do local t=e[1]; local x=(t=="d")
|
||||
rows[#rows+1]=emit1("SVE_INSR", string.format("{.%s, .%s, .NONE, .NONE}",e[2], x and "X_REG" or "W_REG"),
|
||||
"{.VD, .VN, .NONE, .NONE}", e[3], {31,31},
|
||||
function(v) return string.format("insr z%d.%s, %s", v[1],t, g(v[2],x)) end)
|
||||
end
|
||||
block("SVE_INSR", rows)
|
||||
end
|
||||
-- COMPACT: Zd.T, Pg, Zn.T (S/D)
|
||||
do
|
||||
local rows={}
|
||||
for _,e in ipairs(E_SD) do local t=e[1]
|
||||
rows[#rows+1]=emit1("SVE_COMPACT", string.format("{.%s, .P_REG_GOV, .%s, .NONE}",e[2],e[2]),
|
||||
"{.VD, .PG, .VN, .NONE}", e[3], {31,7,31},
|
||||
function(v) return string.format("compact z%d.%s, p%d, z%d.%s", v[1],t, v[2], v[3],t) end)
|
||||
end
|
||||
block("SVE_COMPACT", rows)
|
||||
end
|
||||
sections[#sections+1] = "\t// SVE predicated / compare / predicate-logical / SVE2.\n" .. table.concat(blk, "\n")
|
||||
end
|
||||
|
||||
-- ---- splice into the SoT ---------------------------------------------------
|
||||
local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END"
|
||||
local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close()
|
||||
|
||||
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Reference in New Issue
Block a user