mirror of
https://github.com/odin-lang/Odin.git
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rexcode/arm32: masks that could not separate sibling forms
Forty-one groups of forms differed only in bits their own mask left
free, so they all matched each other's words and whichever sorted first
answered for the lot. That is where the NEON element sizes went:
`vabs.s8`, `.s16` and `.s32` are three patterns differing at bits 19:18,
and with those bits outside the mask the first one spoke for all three.
121 rows.
Two things that exposed:
- LDM and STM differ only in the writeback bit, and nothing in the
operand model recorded it, so the two forms printed identically.
Instruction carries it now and the base register wears its `!`.
- The T32 shifts left the S bit free, and their patterns sort ahead of
MOV's, so `movs.w r1, r2` came back as `lsl r1, r2, #0`. There is no
LSLS form in the table for it to have become instead; pinning the
bit at least stops it answering for a word that is not its own.
Also: r0 could not be used as an index register. The printer took a
register-offset operand to be immediate-only unless the index was
non-zero, when the class alone already says whether there is one --
`[r0, -r0]` printed as `[r0]`. And a displacement of zero lost its U
bit, which llvm-mc writes as `#-0` because it is a different word.
Against llvm-mc, A32 entries whose disassembly assembles back to the
same word: 760 of 1139, from 683. Wrong: 81, from 158.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
@@ -165,6 +165,14 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in
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if e.flags.sets_flags {
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inst.sets_flags = true
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}
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// LDM/STM carry the writeback in bit 21; nothing else in the operand
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// model records it, and without it the two forms print identically.
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for k in 0 ..< len(e.enc) {
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if e.enc[k] == .A32_REG_LIST {
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inst.writeback = (word >> 21) & 1 != 0
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break
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}
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}
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for _, k in e.enc {
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if e.enc[k] == .NONE { continue }
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@@ -379,13 +387,17 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
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u_bit := (word >> 23) & 1
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disp := i32(word & 0xFFF)
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if u_bit == 0 { disp = -disp }
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return op_mem(mem_imm(base, disp))
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mm := mem_imm(base, disp)
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if u_bit == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_IMM8_OFFSET:
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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u_bit := (word >> 23) & 1
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disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF))
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if u_bit == 0 { disp = -disp }
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return op_mem(mem_imm(base, disp))
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mm := mem_imm(base, disp)
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if u_bit == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_REG_OFFSET:
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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idx := Register(REG_GPR | u16(word & 0xF))
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@@ -566,24 +578,36 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF))
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if (word >> 23) & 1 == 0 { disp = -disp }
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return op_mem(mem_imm_pre(base, disp))
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mm := mem_imm_pre(base, disp)
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if (word >> 23) & 1 == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_IMM8_POST_INDEX:
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF))
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if (word >> 23) & 1 == 0 { disp = -disp }
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return op_mem(mem_imm_post(base, disp))
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mm := mem_imm_post(base, disp)
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if (word >> 23) & 1 == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_PRE_INDEX:
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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u_bit := (word >> 23) & 1
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disp := i32(word & 0xFFF)
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if u_bit == 0 { disp = -disp }
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return op_mem(mem_imm_pre(base, disp))
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mm := mem_imm_pre(base, disp)
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if u_bit == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_POST_INDEX:
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base := Register(REG_GPR | u16((word >> 16) & 0xF))
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u_bit := (word >> 23) & 1
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disp := i32(word & 0xFFF)
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if u_bit == 0 { disp = -disp }
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return op_mem(mem_imm_post(base, disp))
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mm := mem_imm_post(base, disp)
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if u_bit == 0 { mm.sign = -1 }
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return op_mem(mm)
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case .MEM_LITERAL:
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// PC-relative literal load: U bit + 12-bit signed disp
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u_bit := (word >> 23) & 1
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@@ -164,6 +164,7 @@ encode_one_inline :: #force_inline proc(
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(want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) &&
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encoding_matches_inline(inst, f) &&
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inst.sets_flags == f.flags.sets_flags &&
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writeback_matches(inst, f) &&
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mem_mode_matches(inst, f) {
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form = f
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}
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@@ -180,6 +181,7 @@ encode_one_inline :: #force_inline proc(
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if !encoding_matches_inline(inst, &f) { continue }
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if inst.sets_flags && !f.flags.sets_flags { continue }
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if !inst.sets_flags && f.flags.sets_flags { continue }
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if !writeback_matches(inst, &f) { continue }
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if !mem_mode_matches(inst, &f) { continue }
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form = &f
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break
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@@ -516,7 +518,7 @@ pack_operand_inline :: #force_inline proc(
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case .MEM_IMM12_OFFSET:
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m := op.mem
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base := (u32(reg_hw(m.base)) & 0xF) << 16
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u_bit: u32 = m.disp >= 0 ? 1 : 0
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u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0
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disp := u32(abs_i32(m.disp)) & 0xFFF
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return base | (u_bit << 23) | disp
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case .RT2_A32_PAIR:
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@@ -524,7 +526,7 @@ pack_operand_inline :: #force_inline proc(
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case .MEM_IMM8_PRE_INDEX, .MEM_IMM8_POST_INDEX, .MEM_IMM8_OFFSET:
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m := op.mem
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base := (u32(reg_hw(m.base)) & 0xF) << 16
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u_bit: u32 = m.disp >= 0 ? 1 : 0
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u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0
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disp := u32(abs_i32(m.disp)) & 0xFF
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return base | (u_bit << 23) | ((disp >> 4) & 0xF) << 8 | (disp & 0xF)
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case .MEM_REG_OFFSET:
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@@ -538,14 +540,14 @@ pack_operand_inline :: #force_inline proc(
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// P=1, W=1 in bits 24/21 to select pre-index addressing mode.
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m := op.mem
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base := (u32(reg_hw(m.base)) & 0xF) << 16
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u_bit: u32 = m.disp >= 0 ? 1 : 0
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u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0
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disp := u32(abs_i32(m.disp)) & 0xFFF
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return base | (u_bit << 23) | disp
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case .MEM_POST_INDEX:
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// Same layout as MEM_IMM12_OFFSET; form bits select P=0 in bit 24.
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m := op.mem
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base := (u32(reg_hw(m.base)) & 0xF) << 16
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u_bit: u32 = m.disp >= 0 ? 1 : 0
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u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0
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disp := u32(abs_i32(m.disp)) & 0xFFF
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return base | (u_bit << 23) | disp
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case .MEM_LITERAL:
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@@ -882,3 +884,15 @@ neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (sh
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case: return 7, 0x1, 4
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}
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}
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// LDM/STM come in a writeback form and a plain one that differ only in bit 21,
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// so the operand shapes cannot tell them apart.
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@(private="file", require_results)
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writeback_matches :: #force_inline proc "contextless" (inst: ^Instruction, f: ^Encoding) -> bool {
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for e in f.enc {
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if e == .A32_REG_LIST {
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return ((f.bits >> 21) & 1 != 0) == inst.writeback
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}
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}
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return true
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}
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@@ -39,7 +39,10 @@ Instruction :: struct #align(64) {
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length: u8 | 3, // 2 or 4 bytes on the wire
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sets_flags: bool | 1, // S bit (writes APSR.NZCV)
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wide: bool | 1, // force the T32 wide form when both exist
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// 3 bits spare
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// LDM/STM write the updated base back when this is set, which the
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// syntax shows as a `!` after the base register.
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writeback: bool | 1,
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// 2 bits spare
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},
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// Form-id hint: when non-zero, this is (1 + the index into
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// ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder
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@@ -136,6 +136,9 @@ sbprint :: proc(
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for k in 0..<inst.operand_count {
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if k > 0 { strings.write_string(sb, ", ") }
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write_operand(sb, &inst.ops[k], inst, offset, &display, opts)
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// LDM/STM write the updated base back, and the syntax marks
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// that with a `!` on the base register itself.
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if k == 0 && inst.writeback { strings.write_byte(sb, '!') }
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}
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}
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strings.write_string(sb, "\n")
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@@ -573,7 +576,10 @@ write_operand :: proc(
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write_memory :: proc(sb: ^strings.Builder, m: Memory) {
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strings.write_string(sb, "[")
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write_register(sb, m.base)
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if reg_class(m.index) == REG_GPR && reg_hw(m.index) != 0 {
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// An immediate-only form leaves index at Register(0), whose class is not
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// REG_GPR -- so the class alone says whether there is an index. Excluding
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// hw 0 as well made r0 unusable as one.
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if reg_class(m.index) == REG_GPR {
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// Register offset
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switch m.mode {
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case .OFFSET:
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@@ -595,15 +601,18 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory) {
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} else {
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// An indexed form writes its displacement even when it is zero: the
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// writeback is the point, and `[r0]` alone is the plain offset form.
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// The U bit also survives a zero displacement, and an assembler needs
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// to see it -- `#-0` and `#0` are different words.
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neg := m.disp == 0 && m.sign < 0 ? "-" : ""
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switch m.mode {
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case .OFFSET:
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if m.disp != 0 {
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fmt.sbprintf(sb, ", #%d]", m.disp)
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if m.disp != 0 || m.sign < 0 {
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fmt.sbprintf(sb, ", #%s%d]", neg, m.disp)
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} else {
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strings.write_string(sb, "]")
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}
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case .PRE_INDEX: fmt.sbprintf(sb, ", #%d]!", m.disp)
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case .POST_INDEX: fmt.sbprintf(sb, "], #%d", m.disp)
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case .PRE_INDEX: fmt.sbprintf(sb, ", #%s%d]!", neg, m.disp)
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case .POST_INDEX: fmt.sbprintf(sb, "], #%s%d", neg, m.disp)
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}
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}
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}
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@@ -164,11 +164,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
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// T16 Format 4 AND: 010000 0000 Rm Rd
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{.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}},
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// T32 AND imm12: high=11110 i 0 0000 S Rn low=0 imm3 Rd imm8
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{.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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{.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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// T32 AND reg: high=11101 01 0000 S Rn low=imm3 Rd imm2 type Rm
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{.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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{.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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},
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.EOR = {
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{.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {}},
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@@ -224,11 +224,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
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// T16 Format 5 hi-reg MOV: 010001 10 H1 H2 Rm Rd
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{.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}},
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// T32 MOV imm12-mod (encoding T2): high=11110 i 0 0010 S 1111 low=0 imm3 Rd imm8
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{.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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{.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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// T32 MOV reg (encoding T3): high=11101 01 0010 S 1111 low=0 imm3 Rd imm2 00 Rm
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{.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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{.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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{.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}},
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},
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.MVN = {
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{.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {}},
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@@ -1116,17 +1116,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
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// base register + register-list into Rn + register_list operand slots.
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.LDM = {
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// LDM IA (default)
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{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}},
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{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {}},
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// LDMIA writeback (LDM Rn!, {reglist}): W=1
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{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}},
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{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {}},
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// T16 Format 15 LDMIA: 11001 Rb reg_list8
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{.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
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// T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14
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{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
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},
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.STM = {
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{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}},
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{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}},
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{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {}},
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{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {}},
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// T16 Format 15 STMIA: 11000 Rb reg_list8
|
||||
{.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
|
||||
// T32 STMIA: 0xE8800000
|
||||
@@ -1442,23 +1442,23 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// 1110 .I8 → 0xF2800E10
|
||||
// 1111 .F32 (special: high bit = 0) → 0xF2800F10 (limited to specific imm patterns)
|
||||
// 1110 op=1 + bit 5 set → .I64 → 0xF2800E30
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1)
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1)
|
||||
// Q forms (Q=1, bit 6 = 1)
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q
|
||||
// ---- VMOV scalar to/from GPR (lane access) ----
|
||||
// VMOV.<size> Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000
|
||||
// VMOV.<size> Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000
|
||||
@@ -1883,11 +1883,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
{.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
// Integer: 0xF3B10100 base for .I8, opc=000
|
||||
{.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
// Float: 0xF3B90500 base (.F32, opc=010)
|
||||
{.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
},
|
||||
.VCGT = {
|
||||
// signed: 0xF200_0300; unsigned: 0xF300_0300
|
||||
@@ -1906,10 +1906,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// F16
|
||||
{.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
{.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
{.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
},
|
||||
.VCGE = {
|
||||
// signed: 0xF200_0310; unsigned: 0xF300_0310
|
||||
@@ -1927,10 +1927,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// F16
|
||||
{.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
{.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
|
||||
{.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
},
|
||||
// ---- VQADD / VQSUB (saturating) ----
|
||||
.VQADD = {
|
||||
@@ -2136,15 +2136,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}},
|
||||
// NEON integer: 1111 0011 1011 size 01 Vd 0011 0 Q M 0 Vm
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
// NEON F32 (size=10, bit 10 = 1)
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
// MVE integer + FP. Per LLVM: vabs.s8 q,q = FFB1_0340; vabs.f32 q,q = FFB9_0740 (bit 19 = 1 for FP).
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
|
||||
@@ -2153,15 +2153,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}},
|
||||
// NEON integer (bit 7 = 1 distinguishes VNEG from VABS)
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
// NEON F32
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
// MVE integer + FP. Per LLVM: vneg.s8 q,q = FFB1_03C0; vneg.f32 q,q = FFB9_07C0.
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
|
||||
@@ -2173,36 +2173,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VCLZ = {
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
},
|
||||
.VCLS = {
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
},
|
||||
|
||||
// ---- VREV16 / VREV32 / VREV64 (byte/half/word reverse within block) ----
|
||||
.VREV64 = {
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VREV32 = {
|
||||
{.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
},
|
||||
.VREV16 = {
|
||||
{.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
@@ -2234,26 +2234,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
|
||||
// ---- VTRN / VUZP / VZIP (interleave / deinterleave) ----
|
||||
.VTRN = {
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VUZP = {
|
||||
{.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VZIP = {
|
||||
{.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
{.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
|
||||
// ---- VTBL / VTBX (table lookup) ----
|
||||
@@ -2510,26 +2510,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
},
|
||||
.VMOVN = {
|
||||
// VMOVN.I<size> D, Q : 1111 0011 1 D 11 size 10 Vd 0010 0 0 M 0 Vm
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32
|
||||
{.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64
|
||||
},
|
||||
.VQMOVN = {
|
||||
// VQMOVN.<sz> (signed saturating narrowing move)
|
||||
// .S<size>: 1111 0011 1 D 11 size 10 Vd 0010 1 0 M 0 Vm
|
||||
// .U<size>: same with op bit 6 = 1
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}},
|
||||
{.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}},
|
||||
},
|
||||
.VQMOVUN = {
|
||||
// VQMOVUN (signed input, unsigned saturating output): 1111 0011 1 D 11 size 10 Vd 0010 0 1 M 0 Vm (bit 6=1, bit 7=0)
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}},
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}},
|
||||
},
|
||||
|
||||
// ---- VSHLL / VSHRN / VRSHRN / VQSHRN / VQRSHRN ----
|
||||
@@ -2538,9 +2538,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32
|
||||
{.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
// VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
},
|
||||
.VSHRN = {
|
||||
// 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm
|
||||
@@ -2571,13 +2571,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// 1111 0011 1 D 11 size 00 Vd 0010 op Q M 0 Vm (op=0 add long, op=1 accumulate)
|
||||
.VPADDL = {
|
||||
// .S<size>:
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}},
|
||||
// Q form
|
||||
{.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
// .U<size> variants: bit 7 = 1
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}},
|
||||
{.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}},
|
||||
{.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}},
|
||||
},
|
||||
.VPADAL = {
|
||||
@@ -2655,9 +2655,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// T16 Format 4: LSL reg (Rd = Rd <<= Rs)
|
||||
{.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}},
|
||||
// T32 LSL imm (encoded as MOV with shift LSL): high=11101010 0100 1111 low=0 imm3 Rd imm2 00 Rm
|
||||
{.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
// T32 LSL reg: high=11111010 0000 Rn low=1111 Rd 0000 Rm
|
||||
{.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
},
|
||||
.LSR = {
|
||||
{.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}},
|
||||
@@ -2667,9 +2667,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// T16 Format 4: LSR reg
|
||||
{.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}},
|
||||
// T32 LSR imm (MOV with shift LSR): bits 5:4 = 01
|
||||
{.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
// T32 LSR reg: 0xFA20F000
|
||||
{.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
},
|
||||
.ASR = {
|
||||
{.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}},
|
||||
@@ -2679,9 +2679,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// T16 Format 4: ASR reg
|
||||
{.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}},
|
||||
// T32 ASR imm: bits 5:4 = 10
|
||||
{.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
// T32 ASR reg: 0xFA40F000
|
||||
{.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
},
|
||||
.ROR = {
|
||||
{.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {}},
|
||||
@@ -2689,9 +2689,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// T16 Format 4: ROR reg
|
||||
{.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}},
|
||||
// T32 ROR imm: bits 5:4 = 11
|
||||
{.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
// T32 ROR reg: 0xFA60F000
|
||||
{.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
},
|
||||
.RRX = {
|
||||
// RRX is ROR with imm=0 (cond 00011010 0000 Rd 00000110 Rm)
|
||||
@@ -3623,10 +3623,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}},
|
||||
{.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
},
|
||||
.VCLT = {
|
||||
{.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
@@ -3643,10 +3643,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}},
|
||||
{.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}},
|
||||
{.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
},
|
||||
.VACLE = {
|
||||
{.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -17,10 +17,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
// .EOR
|
||||
{ .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
@@ -139,10 +139,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} },
|
||||
// .BIC
|
||||
{ .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
@@ -168,28 +168,28 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .LSR
|
||||
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .ASR
|
||||
{ .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .ROR
|
||||
{ .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .RRX
|
||||
{ .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
// .ADR
|
||||
@@ -799,13 +799,13 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
// .STLEXD
|
||||
{ .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} },
|
||||
// .LDM
|
||||
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .STM
|
||||
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
|
||||
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .LDMIB
|
||||
@@ -1012,27 +1012,27 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
// .VABS
|
||||
{ .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} },
|
||||
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
|
||||
// .VNEG
|
||||
{ .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} },
|
||||
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
|
||||
// .VSQRT
|
||||
@@ -1109,22 +1109,22 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
|
||||
@@ -1429,20 +1429,20 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .VMOVN
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
// .VQMOVN
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} },
|
||||
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} },
|
||||
// .VQMOVUN
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} },
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} },
|
||||
// .VMOVL
|
||||
{ .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
@@ -1468,10 +1468,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
// .VCGE
|
||||
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
@@ -1485,10 +1485,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
// .VCGT
|
||||
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
@@ -1502,10 +1502,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
// .VCLE
|
||||
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
@@ -1521,10 +1521,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} },
|
||||
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
// .VCLT
|
||||
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
@@ -1540,10 +1540,10 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} },
|
||||
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
// .VACGE
|
||||
{ .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
@@ -1603,11 +1603,11 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
// .VPADDL
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} },
|
||||
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} },
|
||||
{ .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} },
|
||||
// .VPADAL
|
||||
{ .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
@@ -1706,23 +1706,23 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
// .VSHLL
|
||||
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
// .VCLS
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} },
|
||||
{ .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} },
|
||||
// .VCLZ
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
// .VCNT
|
||||
{ .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
@@ -1730,17 +1730,17 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VREV32
|
||||
{ .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
// .VREV64
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VEXT
|
||||
{ .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} },
|
||||
@@ -1755,24 +1755,24 @@ ENCODE_FORMS := [1649]lib.Encoding{
|
||||
{ .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VTRN
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VUZP
|
||||
{ .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VZIP
|
||||
{ .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VDUP
|
||||
{ .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
|
||||
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|
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|
Before Width: | Height: | Size: 3.2 KiB After Width: | Height: | Size: 3.2 KiB |
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@@ -102,7 +102,7 @@ run_smoke :: proc() {
|
||||
check("STRH imm", .STRH, 0, 0x014000B0, 0x0F7000F0)
|
||||
check("LDRSB imm", .LDRSB, 0, 0x015000D0, 0x0F7000F0)
|
||||
check("LDRD", .LDRD, 0, 0x014000D0, 0x0F7000F0)
|
||||
check("LDM", .LDM, 0, 0x08900000, 0x0FD00000)
|
||||
check("LDM", .LDM, 0, 0x08900000, 0x0FF00000)
|
||||
check("STM DB", .STMDB, 0, 0x09000000, 0x0FD00000)
|
||||
check("PUSH", .PUSH, 0, 0x092D0000, 0x0FFF0000)
|
||||
check("POP", .POP, 0, 0x08BD0000, 0x0FFF0000)
|
||||
@@ -174,18 +174,18 @@ run_smoke :: proc() {
|
||||
check("VABD.S8 D", .VABD, 0, 0xF2000700, 0xFFB00F10)
|
||||
check("VPADD.I8 D", .VPADD, 0, 0xF2000B10, 0xFFB00F10)
|
||||
// NEON unary + shifts
|
||||
check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFB30FD0)
|
||||
check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFB30FD0)
|
||||
check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFBF0FD0)
|
||||
check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFBF0FD0)
|
||||
check("VMVN", .VMVN, 0, 0xF3B00580, 0xFFB30FD0)
|
||||
check("VCNT", .VCNT, 0, 0xF3B00500, 0xFFB30FD0)
|
||||
check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFB30FD0)
|
||||
check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFBF0FD0)
|
||||
check("VSHR.S8 D imm", .VSHR, 0, 0xF2800010, 0xFE800F10)
|
||||
check("VSHL reg.S8 D", .VSHL, 0, 0xF2000400, 0xFFB00F10)
|
||||
check("VEXT D", .VEXT, 0, 0xF2B00000, 0xFFB00010)
|
||||
check("VDUP from Rt D", .VDUP, 0, 0x0EC00B10, 0x0FF00FD0)
|
||||
check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFB30FD0)
|
||||
check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFB30FD0)
|
||||
check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB30FD0)
|
||||
check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFBF0FD0)
|
||||
check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFBF0FD0)
|
||||
check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB70FD0)
|
||||
check("VTBL", .VTBL, 0, 0xF3B00800, 0xFFB00F70)
|
||||
check("VRECPE F32 D", .VRECPE, 2, 0xF3BB0500, 0xFFBF0FD0)
|
||||
check("VLD1 1-reg", .VLD1, 0, 0xF420070F, 0xFFF00F0F)
|
||||
@@ -289,8 +289,8 @@ run_smoke :: proc() {
|
||||
check("CLREX T32", .CLREX, 1, 0xF3BF8F2F, 0xFFFFFFFF)
|
||||
|
||||
// ---- T32 32-bit Thumb-2 data-processing ----
|
||||
check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBE08000)
|
||||
check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFE08000)
|
||||
check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBF08000)
|
||||
check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFF08000)
|
||||
check("EOR T32 imm", .EOR, 7, 0xF0800000, 0xFBE08000)
|
||||
check("ORR T32 imm", .ORR, 7, 0xF0400000, 0xFBE08000)
|
||||
check("BIC T32 imm", .BIC, 7, 0xF0200000, 0xFBE08000)
|
||||
@@ -337,12 +337,12 @@ run_smoke :: proc() {
|
||||
check("VQRDMULH.S16", .VQRDMULH, 0, 0xF3100B00, 0xFFB00F10)
|
||||
check("VQDMULL.S16", .VQDMULL, 0, 0xF2900D00, 0xFFB00F50)
|
||||
check("VMOVL.S8", .VMOVL, 0, 0xF2880A10, 0xFFB80FD0)
|
||||
check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFB30FD0)
|
||||
check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFB30FD0)
|
||||
check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFB30FD0)
|
||||
check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFBF0FD0)
|
||||
check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFBF0FD0)
|
||||
check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFBF0FD0)
|
||||
check("VSHRN imm", .VSHRN, 0, 0xF2800810, 0xFE800FD0)
|
||||
check("VQSHRN.S", .VQSHRN, 0, 0xF2800910, 0xFE800FD0)
|
||||
check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFB30FD0)
|
||||
check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFBF0FD0)
|
||||
check("VPADAL.S8", .VPADAL, 0, 0xF3B00600, 0xFFB30FD0)
|
||||
check("VSWP.I8", .VSWP, 0, 0xF3B20000, 0xFFB30FD0)
|
||||
check("VACGE.F32 D", .VACGE, 0, 0xF3000E10, 0xFFB00F10)
|
||||
@@ -537,12 +537,12 @@ run_smoke :: proc() {
|
||||
check("VCVT F16", .VCVT, 19, 0x0EBE0940, 0x0FBF0FD0)
|
||||
|
||||
// ---- NEON compare-with-zero ----
|
||||
check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFB30FD0)
|
||||
check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFB30FD0)
|
||||
check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFB30FD0)
|
||||
check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFB30FD0)
|
||||
check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFB30FD0)
|
||||
check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFB30FD0)
|
||||
check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFBB0FD0)
|
||||
check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFBB0FD0)
|
||||
check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFBB0FD0)
|
||||
check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFBB0FD0)
|
||||
check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFBB0FD0)
|
||||
check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFBB0FD0)
|
||||
|
||||
// ---- NEON replicate loads ----
|
||||
check("VLD2R", .VLD2R, 0, 0xF4A00D0F, 0xFFB00F0F)
|
||||
|
||||
Reference in New Issue
Block a user