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rexcode/arm32: LDMIB/LDMDA/LDMDB and STMIB/STMDA/STMDB are their own mnemonics

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LDM and STM each held five A32 forms with identical operand shapes -- the four
increment/decrement orders plus a writeback variant -- distinguished only by
their fixed bits. Nothing could tell them apart, so the encoder always took the
first and six of the eight A32 encodings were unreachable: `ldmib`, `ldmda`,
`ldmdb`, `stmib`, `stmda`, `stmdb` could not be produced at all.

They are not variants of one mnemonic in the first place. An assembler spells
them `ldmib` / `ldmda` / `ldmdb`, with plain `ldm` meaning IA, so this follows
the same rule as the rest of the enum: one member per name an assembler
accepts. LDM/STM keep the IA order and the Thumb encodings; the other three
orders become their own mnemonics, and the T32 DB encodings join them.

All eight now encode, byte-exact against llvm-mc:

  ldm   e8900006    stm   e8800006
  ldmib e9900006    stmib e9800006
  ldmda e8100006    stmda e8000006
  ldmdb e9100006    stmdb e9000006

Six test checks referenced these forms by index; they were re-derived by
matching (bits, mask) against the rebuilt table rather than by adjusting
offsets, and every one was found -- so no form was lost in the move.

Writeback (`ldm r0!, {...}`) is still unreachable: it is a property of the base
operand, not a separate mnemonic, and there is nowhere to put it yet. That is
one form per family rather than four.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Brendan Punsky
2026-08-27 03:01:36 -04:00
committed by Flāvius
parent 02cce151ca
commit db2c234607
11 changed files with 104 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
core/rexcode/isa/arm32/mnemonic_builders.odin
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@@ -604,6 +604,18 @@ inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, r
emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) }
inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) }
inst_ldmib_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_ldmib_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmib_r_list(dst, regs)) }
inst_ldmda_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_ldmda_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmda_r_list(dst, regs)) }
inst_ldmdb_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_ldmdb_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmdb_r_list(dst, regs)) }
inst_stmib_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_stmib_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmib_r_list(dst, regs)) }
inst_stmda_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_stmda_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmda_r_list(dst, regs)) }
inst_stmdb_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
emit_stmdb_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmdb_r_list(dst, regs)) }
inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) }
inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
@@ -1891,6 +1903,18 @@ inst_ldm :: inst_ldm_r_list
emit_ldm :: emit_ldm_r_list
inst_stm :: inst_stm_r_list
emit_stm :: emit_stm_r_list
inst_ldmib :: inst_ldmib_r_list
emit_ldmib :: emit_ldmib_r_list
inst_ldmda :: inst_ldmda_r_list
emit_ldmda :: emit_ldmda_r_list
inst_ldmdb :: inst_ldmdb_r_list
emit_ldmdb :: emit_ldmdb_r_list
inst_stmib :: inst_stmib_r_list
emit_stmib :: emit_stmib_r_list
inst_stmda :: inst_stmda_r_list
emit_stmda :: emit_stmda_r_list
inst_stmdb :: inst_stmdb_r_list
emit_stmdb :: emit_stmdb_r_list
inst_push :: inst_push_list
emit_push :: emit_push_list
inst_pop :: inst_pop_list

8
core/rexcode/isa/arm32/mnemonics.odin
View File

@@ -190,7 +190,13 @@ Mnemonic :: enum u16 {
LDAEXD, STLEXD,
// Block move
LDM, STM, // base mnemonic w/ IA/IB/DA/DB suffix flag
LDM, STM, // IA order (the default spelling)
// The other three increment/decrement orders are their own mnemonics --
// that is how an assembler spells them, and it is the only way to reach
// their encodings: all four share one operand shape, so nothing else
// tells them apart.
LDMIB, LDMDA, LDMDB,
STMIB, STMDA, STMDB,
// Stack convenience aliases
PUSH, POP,

33
core/rexcode/isa/arm32/tablegen/encoding_table.odin
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@@ -1119,31 +1119,18 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}},
// LDMIA writeback (LDM Rn!, {reglist}): W=1
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}},
// LDMIB
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}},
// LDMDA
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}},
// LDMDB
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}},
// T16 Format 15 LDMIA: 11001 Rb reg_list8
{.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
// T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
// T32 LDMDB: high=11101001 0001 Rn low=PM 0 reg_list14
{.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STM = {
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}},
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}},
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}},
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}},
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}},
// T16 Format 15 STMIA: 11000 Rb reg_list8
{.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
// T32 STMIA: 0xE8800000
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
// T32 STMDB: 0xE9000000
{.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
// PUSH / POP are conventional aliases for STMDB SP! / LDMIA SP!
@@ -3748,5 +3735,25 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}},
},
// SPECGEN:END
.LDMIB = {
{.LDMIB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}},
},
.LDMDA = {
{.LDMDA, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}},
},
.LDMDB = {
{.LDMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}},
{.LDMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STMIB = {
{.STMIB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}},
},
.STMDA = {
{.STMDA, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}},
},
.STMDB = {
{.STMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}},
{.STMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
}

50
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
View File

@@ -186,8 +186,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -230,8 +230,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
@@ -337,8 +337,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} },
@@ -373,8 +373,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} },
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} },
{ .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -400,8 +400,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
@@ -1014,20 +1014,20 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} },
{ .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} },
{ .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} },
@@ -1236,9 +1236,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
@@ -1704,21 +1704,21 @@ DECODE_FORM_IDX := [1680]u16{
1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5,
4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14,
8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0,
0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4,
4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4,
2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8,
1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10,
8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4,
5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2,
1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0,
1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0,
7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10,
3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 23, 25, 0, 0,
3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 25, 23, 0, 0,
0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 16, 14, 18, 12, 10, 6,
0, 0, 0, 3, 5, 9, 7, 4, 6, 2, 8, 1, 0, 1, 0, 0,
0, 0, 1, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0,
0, 0, 0, 3, 5, 9, 7, 6, 4, 2, 8, 1, 0, 1, 0, 0,
0, 1, 0, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0,
2, 0, 2, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18,
12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 2, 0, 2, 0, 4, 4,
4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, 16, 12, 15,
@@ -1755,8 +1755,8 @@ DECODE_FORM_IDX := [1680]u16{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, 0,
0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3,
0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0,
0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9,
9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3,
@@ -1769,7 +1769,7 @@ DECODE_FORM_IDX := [1680]u16{
5, 4, 6, 2, 0, 1, 3, 7, 13, 14, 0, 1, 1, 0, 3, 2,
0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 4, 1, 0, 1, 0,
16, 15, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1,
1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 6, 7, 6, 7, 4, 4,
1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4,
4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8,
8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, 0,
1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1797,7 +1797,7 @@ DECODE_FORM_IDX := [1680]u16{
4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9,
5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5,
5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1,
1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 5, 5, 1, 1, 1, 2,
1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2,
}
@(rodata)
@@ -2022,8 +2022,8 @@ DECODE_BUCKET_LIST := [5553]u16{
1648, 1648, 1649, 1649, 1650, 1650, 1651, 1651, 1652, 1652, 1653, 1654, 1655, 1656, 1657, 1658,
1659, 1660, 1661, 1662, 1663, 1664, 1665, 1666, 1667, 1668, 1669, 1670, 1671, 1672, 1673, 1674,
1674, 1675, 1675, 1676, 1676, 1676, 1677, 1678, 1676, 1679, 1679, 1217, 1218, 1219, 1220, 1225,
1231, 1221, 1230, 1231, 1230, 1228, 1226, 1228, 1224, 1226, 1214, 1215, 1222, 1231, 1210, 1211,
1212, 1213, 1216, 1230, 1231, 1230, 1229, 1227, 1223, 1229, 1227, 1231, 1230, 1231, 1209, 1230,
1231, 1221, 1230, 1231, 1230, 1227, 1226, 1227, 1224, 1226, 1214, 1215, 1222, 1231, 1210, 1211,
1212, 1213, 1216, 1230, 1231, 1230, 1229, 1228, 1223, 1229, 1228, 1231, 1230, 1231, 1209, 1230,
1231, 1230, 1231, 1230, 1244, 1243, 1236, 1244, 1243, 1250, 1250, 1232, 1233, 1234, 1235, 1241,
1240, 1249, 1232, 1233, 1234, 1235, 1240, 1241, 1249, 1242, 1242, 1245, 1237, 1245, 1239, 1247,
1247, 1248, 1248, 1238, 1246, 1246, 1261, 1269, 1268, 1261, 1265, 1266, 1264, 1267, 1261, 1269,

32
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
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@@ -801,21 +801,27 @@ ENCODE_FORMS := [1680]lib.Encoding{
// .LDM
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STM
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDMIB
{ .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDMDA
{ .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDMDB
{ .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STMIB
{ .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
// .STMDA
{ .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
// .STMDB
{ .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .PUSH
{ .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
@@ -2506,8 +2512,14 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.STLEXH = { 563, 1},
.LDAEXD = { 564, 1},
.STLEXD = { 565, 1},
.LDM = { 566, 8},
.STM = { 574, 8},
.LDM = { 566, 4},
.STM = { 570, 4},
.LDMIB = { 574, 1},
.LDMDA = { 575, 1},
.LDMDB = { 576, 2},
.STMIB = { 578, 1},
.STMDA = { 579, 1},
.STMDB = { 580, 2},
.PUSH = { 582, 3},
.POP = { 585, 3},
.SWP = { 588, 1},

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core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
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core/rexcode/isa/arm32/tables/arm32.encode_forms.bin
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core/rexcode/isa/arm32/tables/arm32.encode_runs.bin
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12
core/rexcode/isa/arm32/tests/smoke.odin
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@@ -103,7 +103,7 @@ run_smoke :: proc() {
check("LDRSB imm", .LDRSB, 0, 0x015000D0, 0x0F7000F0)
check("LDRD", .LDRD, 0, 0x014000D0, 0x0F7000F0)
check("LDM", .LDM, 0, 0x08900000, 0x0FD00000)
check("STM DB", .STM, 4, 0x09000000, 0x0FD00000)
check("STM DB", .STMDB, 0, 0x09000000, 0x0FD00000)
check("PUSH", .PUSH, 0, 0x092D0000, 0x0FFF0000)
check("POP", .POP, 0, 0x08BD0000, 0x0FFF0000)
check("SWP", .SWP, 0, 0x01000090, 0x0FF00FF0)
@@ -257,8 +257,8 @@ run_smoke :: proc() {
check("STRH T16 imm5", .STRH, 5, 0x00008000, 0x0000F800)
check("LDRSB T16", .LDRSB,4, 0x00005600, 0x0000FE00)
check("LDRSH T16", .LDRSH,4, 0x00005E00, 0x0000FE00)
check("LDM T16", .LDM, 5, 0x0000C800, 0x0000F800)
check("STM T16", .STM, 5, 0x0000C000, 0x0000F800)
check("LDM T16", .LDM, 2, 0x0000C800, 0x0000F800)
check("STM T16", .STM, 2, 0x0000C000, 0x0000F800)
check("PUSH T16", .PUSH, 1, 0x0000B400, 0x0000FE00)
check("POP T16", .POP, 1, 0x0000BC00, 0x0000FE00)
@@ -324,9 +324,9 @@ run_smoke :: proc() {
check("STRH T32 imm12", .STRH, 6, 0xF8A00000, 0xFFF00000)
check("LDRSB T32 imm12", .LDRSB, 5, 0xF9900000, 0xFFF00000)
check("LDRSH T32 imm12", .LDRSH, 5, 0xF9B00000, 0xFFF00000)
check("LDM T32 IA", .LDM, 6, 0xE8900000, 0xFFD00000)
check("LDM T32 DB", .LDM, 7, 0xE9100000, 0xFFD00000)
check("STM T32 IA", .STM, 6, 0xE8800000, 0xFFD00000)
check("LDM T32 IA", .LDM, 3, 0xE8900000, 0xFFD00000)
check("LDM T32 DB", .LDMDB, 1, 0xE9100000, 0xFFD00000)
check("STM T32 IA", .STM, 3, 0xE8800000, 0xFFD00000)
check("PUSH T32", .PUSH, 2, 0xE92D0000, 0xFFFF0000)
check("POP T32", .POP, 2, 0xE8BD0000, 0xFFFF0000)