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VMLA, VMUL, VMLAL, VQDMULL, VSDOT, VCMLA and the rest of the by-scalar family take one lane of a low D register as the multiplier -- `d0[2]`, not `d0`. Every one of them printed the bare register, which is not only missing information but assembles to a different instruction: the by-vector form. The forms already declared the operand type as DPR_ELEM; what they lacked was an encoding that knows the register number and the lane number share a single four-bit field. How they share it depends on the element size, and the two splits are different enough to be separate encodings: 16-bit takes Vm from bits 2:0, so D0..D7, and the lane from M:bit3, giving four lanes; 32-bit takes Vm from bits 3:0, so D0..D15, and the lane from M alone, giving two. The dot-product and complex forms share the 32-bit split despite being 8- and 16-bit operations. Those reaches are now checked when selecting a form, so `d8[0]` on a 16-bit form matches nothing rather than quietly encoding as `d0[0]`, and a lane-less operand no longer matches a by-scalar form at all. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA