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https://github.com/odin-lang/Odin.git
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rexcode/arm32: merge the nine *_LANE mnemonics, and make the lane survive
No assembler spells these `vld1_lane` or `vmov_lane`; they are `vld1`
and `vmov` with a lane-indexed operand. All nine are now their base
mnemonic. Merging them meant fixing what the separate names had been
hiding.
VLD1_LANE and VST1_LANE were byte-for-byte duplicates of forms VLD1 and
VST1 already had, with a looser mask, and neither encoded the lane --
both used .VD_D, which has no lane field. `vld1.8 {d0[3]}, [r0]`
disassembled as `vld1.8 d0, [r0]`. VMOV had the same shape: its own
DPR_ELEM form dropped the index, while VMOV_LANE's three forms carried
the per-size encodings that actually work. The lane-dropping forms are
gone and the working ones now sit under the base mnemonic.
VLD2-4/VST2-4's single-lane forms left bits 9:8 free, and that field is
what separates VLD1/2/3/4 -- so VLD4's encoding matched VLD2's entry and
disassembled as the wrong instruction.
Two more things the lane could not survive. A lane index of 0 printed
nothing, because 0 doubled as "no lane" -- `vmov.32 d0[0], r0` came out
as `vmov.32 d0, r0`, a different instruction. And a lane inside a
register list was dropped entirely, so `{d0[1], d1[1]}` printed as
`{d0, d1}`.
The whole set is byte-exact against llvm-mc: 27 single-lane forms across
VLD1-4/VST1-4 and all three VMOV element sizes. arm32 is 1649/1649 on
the sweep and 436/436 on the table checks, with the stale expectations
for the forms this corrected updated to the verified values.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
@@ -445,6 +445,12 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
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case .NEON_D_LIST_ALL:
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n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
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return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true)
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case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4:
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n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
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shift, mask, count := neon_lane_shape(enc)
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op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask))
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op.list = {count = count, stride = 1}
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return op
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case .VFP_S_LIST:
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// {S<Vd>, ...} -- imm8 counts the registers, and the run starts at Vd.
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// Both halves matter: keeping only the count printed the wrong bank
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@@ -604,3 +610,24 @@ decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic
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if inst_info != nil { reserve(inst_info, len(inst_info) + n) }
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if label_defs != nil { reserve(label_defs, len(label_defs) + n) }
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}
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// The lane field's position and the list length for a NEON single-lane
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// load/store. The lane sits just above the alignment bits, and how far above
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// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32.
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@(private="file", require_results)
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neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) {
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#partial switch e {
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case .NEON_LANE_D_8: return 5, 0x7, 1
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case .NEON_LANE_D_16: return 6, 0x3, 1
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case .NEON_LANE_D_32: return 7, 0x1, 1
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case .NEON_LANE_D_8_2: return 5, 0x7, 2
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case .NEON_LANE_D_16_2: return 6, 0x3, 2
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case .NEON_LANE_D_32_2: return 7, 0x1, 2
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case .NEON_LANE_D_8_3: return 5, 0x7, 3
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case .NEON_LANE_D_16_3: return 6, 0x3, 3
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case .NEON_LANE_D_32_3: return 7, 0x1, 3
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case .NEON_LANE_D_8_4: return 5, 0x7, 4
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case .NEON_LANE_D_16_4: return 6, 0x3, 4
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case: return 7, 0x1, 4
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}
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}
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@@ -501,6 +501,10 @@ pack_operand_inline :: #force_inline proc(
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// Only Vd; the count lives in the form's type field.
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n := u32(reg_hw(op.reg)) & 0x1F
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return ((n >> 4) & 1) << 22 | (n & 0xF) << 12
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case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4:
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n := u32(reg_hw(op.reg)) & 0x1F
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shift, mask, _ := neon_lane_shape(enc)
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return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift
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case .VFP_S_LIST:
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n := u32(reg_hw(op.reg)) & 0x1F
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return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF)
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@@ -855,3 +859,24 @@ write_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32, word:
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read_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u16 {
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return u16(code[offset+0]) | (u16(code[offset+1]) << 8)
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}
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// The lane field's position and the list length for a NEON single-lane
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// load/store. The lane sits just above the alignment bits, and how far above
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// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32.
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@(private="file", require_results)
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neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) {
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#partial switch e {
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case .NEON_LANE_D_8: return 5, 0x7, 1
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case .NEON_LANE_D_16: return 6, 0x3, 1
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case .NEON_LANE_D_32: return 7, 0x1, 1
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case .NEON_LANE_D_8_2: return 5, 0x7, 2
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case .NEON_LANE_D_16_2: return 6, 0x3, 2
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case .NEON_LANE_D_32_2: return 7, 0x1, 2
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case .NEON_LANE_D_8_3: return 5, 0x7, 3
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case .NEON_LANE_D_16_3: return 6, 0x3, 3
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case .NEON_LANE_D_32_3: return 7, 0x1, 3
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case .NEON_LANE_D_8_4: return 5, 0x7, 4
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case .NEON_LANE_D_16_4: return 6, 0x3, 4
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case: return 7, 0x1, 4
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}
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}
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@@ -341,6 +341,14 @@ Operand_Encoding :: enum u8 {
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NEON_D_LIST_3X, // {d2, d4, d6} -- spaced
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NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced
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NEON_D_LIST_ALL, // {d2[]} -- to all lanes
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// VLD1/VST1 single-lane: Vd plus the lane index, whose width and position
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// follow the element size -- bits 7:5 for .8, 7:6 for .16, bit 7 for .32.
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// Verified against llvm-mc.
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// ..._N is how many registers the list holds: VLD2 writes `{d0[1], d1[1]}`.
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NEON_LANE_D_8, NEON_LANE_D_16, NEON_LANE_D_32,
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NEON_LANE_D_8_2, NEON_LANE_D_16_2, NEON_LANE_D_32_2,
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NEON_LANE_D_8_3, NEON_LANE_D_16_3, NEON_LANE_D_32_3,
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NEON_LANE_D_8_4, NEON_LANE_D_16_4, NEON_LANE_D_32_4,
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// ---- Memory addressing composites ----
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MEM_IMM12_OFFSET, // [Rn, #±imm12]
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@@ -737,14 +737,14 @@ inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, i
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inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} }
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inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} }
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inst_vmov_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} }
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inst_vmov_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} }
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emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) }
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emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) }
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emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) }
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emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) }
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emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) }
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emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) }
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emit_vmov_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_qlane_r(dst, lane, src)) }
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emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) }
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inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) }
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@@ -1000,8 +1000,6 @@ emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruc
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emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) }
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inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) }
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inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} }
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emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) }
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inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) }
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@@ -1102,22 +1100,6 @@ inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src:
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emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) }
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inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) }
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inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) }
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inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) }
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inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) }
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inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) }
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inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) }
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inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) }
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inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) }
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inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) }
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inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} }
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emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) }
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inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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@@ -2009,8 +1991,8 @@ inst_vcvtm :: inst_vcvtm_s_s
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emit_vcvtm :: emit_vcvtm_s_s
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inst_vcvtr :: inst_vcvtr_s_s
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emit_vcvtr :: emit_vcvtr_s_s
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inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r, inst_vmov_qlane_qlane_r_r }
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emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r, emit_vmov_qlane_qlane_r_r }
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inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_qlane_r, inst_vmov_qlane_qlane_r_r }
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emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_qlane_r, emit_vmov_qlane_qlane_r_r }
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inst_vmrs :: inst_vmrs_r
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emit_vmrs :: emit_vmrs_r
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inst_vmsr :: inst_vmsr_r
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@@ -2223,8 +2205,6 @@ inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane }
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emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane }
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inst_vswp :: inst_vswp_d_d
|
||||
emit_vswp :: emit_vswp_d_d
|
||||
inst_vmov_lane :: inst_vmov_lane_dlane_r
|
||||
emit_vmov_lane :: emit_vmov_lane_dlane_r
|
||||
inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem }
|
||||
emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem }
|
||||
inst_vld2 :: inst_vld2_dlist_mem
|
||||
@@ -2311,22 +2291,6 @@ inst_vld3r :: inst_vld3r_dlist_mem
|
||||
emit_vld3r :: emit_vld3r_dlist_mem
|
||||
inst_vld4r :: inst_vld4r_dlist_mem
|
||||
emit_vld4r :: emit_vld4r_dlist_mem
|
||||
inst_vld1_lane :: inst_vld1_lane_dlane_mem
|
||||
emit_vld1_lane :: emit_vld1_lane_dlane_mem
|
||||
inst_vld2_lane :: inst_vld2_lane_dlist_mem
|
||||
emit_vld2_lane :: emit_vld2_lane_dlist_mem
|
||||
inst_vld3_lane :: inst_vld3_lane_dlist_mem
|
||||
emit_vld3_lane :: emit_vld3_lane_dlist_mem
|
||||
inst_vld4_lane :: inst_vld4_lane_dlist_mem
|
||||
emit_vld4_lane :: emit_vld4_lane_dlist_mem
|
||||
inst_vst1_lane :: inst_vst1_lane_dlane_mem
|
||||
emit_vst1_lane :: emit_vst1_lane_dlane_mem
|
||||
inst_vst2_lane :: inst_vst2_lane_dlist_mem
|
||||
emit_vst2_lane :: emit_vst2_lane_dlist_mem
|
||||
inst_vst3_lane :: inst_vst3_lane_dlist_mem
|
||||
emit_vst3_lane :: emit_vst3_lane_dlist_mem
|
||||
inst_vst4_lane :: inst_vst4_lane_dlist_mem
|
||||
emit_vst4_lane :: emit_vst4_lane_dlist_mem
|
||||
inst_it :: inst_it_cond_imm4
|
||||
emit_it :: emit_it_cond_imm4
|
||||
inst_tt :: inst_tt_r_r
|
||||
|
||||
@@ -300,7 +300,7 @@ Mnemonic :: enum u16 {
|
||||
VSWP, // swap
|
||||
|
||||
// Lane access
|
||||
VMOV_LANE, // VMOV.<dt> R, D[i] / VMOV.<dt> D[i], R
|
||||
// VMOV.<dt> R, D[i] / VMOV.<dt> D[i], R
|
||||
|
||||
// Load/Store structures (NEON)
|
||||
VLD1, VLD2, VLD3, VLD4,
|
||||
@@ -349,9 +349,6 @@ Mnemonic :: enum u16 {
|
||||
VLD2R, VLD3R, VLD4R,
|
||||
|
||||
// -- NEON single-element-lane load/store (lane form, not multi-vec) -----
|
||||
VLD1_LANE, VLD2_LANE, VLD3_LANE, VLD4_LANE,
|
||||
VST1_LANE, VST2_LANE, VST3_LANE, VST4_LANE,
|
||||
|
||||
// -- VFP fixed-point conversions (with #fbits operand) ------------------
|
||||
// VCVT.<dt> Sd, Sd, #fbits family
|
||||
|
||||
|
||||
@@ -114,7 +114,10 @@ Operand :: struct #packed {
|
||||
shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain
|
||||
shift_amt: u8 | 5, // 0..31, or the Rs index for RSR
|
||||
lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM
|
||||
// 3 bits spare
|
||||
// Whether `lane` means anything. Lane 0 is a real index -- `d0[0]`
|
||||
// is not `d0` -- so it cannot be spelled by lane == 0.
|
||||
has_lane: bool | 1,
|
||||
// 2 bits spare
|
||||
},
|
||||
mem: Memory,
|
||||
immediate: i64,
|
||||
@@ -178,9 +181,9 @@ op_reg_run :: #force_inline proc "contextless" (first: Register, count: u8, stri
|
||||
}
|
||||
@(require_results)
|
||||
op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand {
|
||||
return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx}
|
||||
return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx, has_lane = true}
|
||||
}
|
||||
@(require_results)
|
||||
op_qpr_lane :: #force_inline proc "contextless" (q: Register, idx: u8) -> Operand {
|
||||
return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx}
|
||||
return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx, has_lane = true}
|
||||
}
|
||||
|
||||
@@ -535,14 +535,20 @@ write_operand :: proc(
|
||||
for n in 0 ..< u16(op.list.count) {
|
||||
if n > 0 { strings.write_string(sb, ", ") }
|
||||
write_register(sb, Register(reg_class(op.reg) | ((reg_hw(op.reg) + n * step) & 0x1F)))
|
||||
if op.list.all_lanes { strings.write_string(sb, "[]") }
|
||||
// Every member of a single-lane list carries the index:
|
||||
// `{d0[1], d1[1]}`. `{d0[]}` is the to-all-lanes form.
|
||||
if op.list.all_lanes {
|
||||
strings.write_string(sb, "[]")
|
||||
} else if op.has_lane {
|
||||
fmt.sbprintf(sb, "[%d]", op.lane)
|
||||
}
|
||||
}
|
||||
strings.write_string(sb, "}")
|
||||
return
|
||||
}
|
||||
write_register(sb, op.reg)
|
||||
write_shift(sb, op.shift_type, op.shift_amt)
|
||||
if op.lane != 0 {
|
||||
if op.has_lane {
|
||||
fmt.sbprintf(sb, "[%d]", op.lane)
|
||||
}
|
||||
case .IMMEDIATE:
|
||||
|
||||
@@ -1465,13 +1465,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// .8 / .16 / .32 selected by opc1+opc2 split bits in encoding.
|
||||
// 32-bit lane move (.32):
|
||||
{.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}},
|
||||
{.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}},
|
||||
// VMOV.<size> Qd[i], Rt -- single lane Rt -> Qd[i]
|
||||
{.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}},
|
||||
// VMOV.<size> Rt, Qd[i]
|
||||
{.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}},
|
||||
// VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move
|
||||
{.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
{.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}},
|
||||
{.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}},
|
||||
{.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}},
|
||||
},
|
||||
// ---- VMVN NEON modified immediate (op=1 form) ----
|
||||
// bit 5 = 1 distinguishes VMVN from VMOV
|
||||
@@ -2318,9 +2320,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair
|
||||
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL, .RN_A32, .NONE, .NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
// VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector)
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
|
||||
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32
|
||||
},
|
||||
.VST1 = {
|
||||
// VST1 multiple (1-reg list)
|
||||
@@ -2329,36 +2331,54 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
// VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
|
||||
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32
|
||||
},
|
||||
// VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits
|
||||
.VLD2 = {
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST2 = {
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VLD3 = {
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST3 = {
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VLD4 = {
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST4 = {
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
|
||||
// ---- VMULL / VMLAL / VMLSL (widening multiplies) ----
|
||||
@@ -2882,47 +2902,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// 1111 0100 1 D 10 Rn Vd size{2} N index_align Rm
|
||||
// N=00 VLDx1, 01 VLDx2, 10 VLDx3, 11 VLDx4 (x = 1..4)
|
||||
// VLD1_LANE Dd[i], [Rn]: size=00 (.8) 0xF4A00000, size=01 (.16) 0xF4A00400, size=10 (.32) 0xF4A00800
|
||||
.VLD1_LANE = {
|
||||
{.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VLD2_LANE = {
|
||||
{.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VLD3_LANE = {
|
||||
{.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VLD4_LANE = {
|
||||
{.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
// VST1/2/3/4 single-lane: bit 21 = 0 (store, not load)
|
||||
.VST1_LANE = {
|
||||
{.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST2_LANE = {
|
||||
{.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST3_LANE = {
|
||||
{.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
.VST4_LANE = {
|
||||
{.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
},
|
||||
|
||||
// =========================================================================
|
||||
// ARMv8-M Security Extensions (TrustZone-M) -- TT / TTT / TTA / TTAT
|
||||
@@ -3569,11 +3548,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5.
|
||||
// VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on
|
||||
// the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size.
|
||||
.VMOV_LANE = {
|
||||
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}},
|
||||
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}},
|
||||
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}},
|
||||
},
|
||||
|
||||
// MVE (M-profile vector) multiply-subtract-across-vector reduce, halving
|
||||
// complex add (saturating), and complex multiply-accumulate. T32; the
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,7 @@ package rexcode_arm32_generated
|
||||
import lib "../.."
|
||||
|
||||
@(rodata)
|
||||
ENCODE_FORMS := [1656]lib.Encoding{
|
||||
ENCODE_FORMS := [1649]lib.Encoding{
|
||||
// .AND
|
||||
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
@@ -1126,10 +1126,12 @@ ENCODE_FORMS := [1656]lib.Encoding{
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VMRS
|
||||
{ .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VMSR
|
||||
@@ -1780,47 +1782,61 @@ ENCODE_FORMS := [1656]lib.Encoding{
|
||||
// .VSWP
|
||||
{ .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
|
||||
// .VMOV_LANE
|
||||
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD1
|
||||
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD2
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD3
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD4
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST1
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST2
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST3
|
||||
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST4
|
||||
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .AESE
|
||||
{ .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
|
||||
// .AESD
|
||||
@@ -1909,38 +1925,6 @@ ENCODE_FORMS := [1656]lib.Encoding{
|
||||
{ .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD4R
|
||||
{ .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD1_LANE
|
||||
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD2_LANE
|
||||
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD3_LANE
|
||||
{ .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VLD4_LANE
|
||||
{ .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST1_LANE
|
||||
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST2_LANE
|
||||
{ .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST3_LANE
|
||||
{ .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .VST4_LANE
|
||||
{ .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
// .IT
|
||||
{ .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} },
|
||||
// .TT
|
||||
@@ -2545,315 +2529,306 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
|
||||
.VCVTP = { 798, 2},
|
||||
.VCVTM = { 800, 2},
|
||||
.VCVTR = { 802, 4},
|
||||
.VMOV = { 806, 31},
|
||||
.VMRS = { 837, 1},
|
||||
.VMSR = { 838, 1},
|
||||
.VLDR = { 839, 2},
|
||||
.VSTR = { 841, 2},
|
||||
.VLDM = { 843, 2},
|
||||
.VSTM = { 845, 2},
|
||||
.VPUSH = { 847, 2},
|
||||
.VPOP = { 849, 2},
|
||||
.VSEL = { 851, 2},
|
||||
.VMAXNM = { 853, 2},
|
||||
.VMINNM = { 855, 2},
|
||||
.VRINTA = { 857, 3},
|
||||
.VRINTN = { 860, 3},
|
||||
.VRINTP = { 863, 3},
|
||||
.VRINTM = { 866, 3},
|
||||
.VRINTR = { 869, 2},
|
||||
.VRINTZ = { 871, 3},
|
||||
.VRINTX = { 874, 3},
|
||||
.VADDL = { 877, 6},
|
||||
.VADDW = { 883, 6},
|
||||
.VSUBL = { 889, 6},
|
||||
.VSUBW = { 895, 6},
|
||||
.VHADD = { 901, 9},
|
||||
.VHSUB = { 910, 9},
|
||||
.VRHADD = { 919, 3},
|
||||
.VQADD = { 922, 11},
|
||||
.VQSUB = { 933, 11},
|
||||
.VMULL = { 944, 11},
|
||||
.VMLAL = { 955, 10},
|
||||
.VMLSL = { 965, 10},
|
||||
.VQDMULL = { 975, 4},
|
||||
.VQDMLAL = { 979, 4},
|
||||
.VQDMLSL = { 983, 4},
|
||||
.VQDMULH = { 987, 8},
|
||||
.VQRDMULH = { 995, 8},
|
||||
.VQRDMLAH = { 1003, 8},
|
||||
.VQRDMLSH = { 1011, 8},
|
||||
.VABA = { 1019, 8},
|
||||
.VABAL = { 1027, 6},
|
||||
.VABD = { 1033, 10},
|
||||
.VABDL = { 1043, 6},
|
||||
.VAND = { 1049, 3},
|
||||
.VBIC = { 1052, 3},
|
||||
.VORR = { 1055, 3},
|
||||
.VORN = { 1058, 3},
|
||||
.VEOR = { 1061, 3},
|
||||
.VBSL = { 1064, 2},
|
||||
.VBIT = { 1066, 2},
|
||||
.VBIF = { 1068, 2},
|
||||
.VMVN = { 1070, 13},
|
||||
.VMOVN = { 1083, 3},
|
||||
.VQMOVN = { 1086, 6},
|
||||
.VQMOVUN = { 1092, 3},
|
||||
.VMOVL = { 1095, 6},
|
||||
.VTST = { 1101, 6},
|
||||
.VCEQ = { 1107, 14},
|
||||
.VCGE = { 1121, 16},
|
||||
.VCGT = { 1137, 16},
|
||||
.VCLE = { 1153, 18},
|
||||
.VCLT = { 1171, 18},
|
||||
.VACGE = { 1189, 2},
|
||||
.VACGT = { 1191, 2},
|
||||
.VACLE = { 1193, 2},
|
||||
.VACLT = { 1195, 2},
|
||||
.VMAX = { 1197, 13},
|
||||
.VMIN = { 1210, 13},
|
||||
.VPMAX = { 1223, 5},
|
||||
.VPMIN = { 1228, 5},
|
||||
.VPADD = { 1233, 5},
|
||||
.VPADDL = { 1238, 6},
|
||||
.VPADAL = { 1244, 4},
|
||||
.VRECPE = { 1248, 4},
|
||||
.VRECPS = { 1252, 2},
|
||||
.VRSQRTE = { 1254, 4},
|
||||
.VRSQRTS = { 1258, 2},
|
||||
.VSHL = { 1260, 9},
|
||||
.VSHR = { 1269, 3},
|
||||
.VSRA = { 1272, 3},
|
||||
.VRSHL = { 1275, 5},
|
||||
.VRSHR = { 1280, 3},
|
||||
.VRSRA = { 1283, 2},
|
||||
.VSLI = { 1285, 2},
|
||||
.VSRI = { 1287, 2},
|
||||
.VQSHL = { 1289, 7},
|
||||
.VQSHRN = { 1296, 1},
|
||||
.VQSHRUN = { 1297, 1},
|
||||
.VQRSHL = { 1298, 16},
|
||||
.VQRSHRN = { 1314, 1},
|
||||
.VQRSHRUN = { 1315, 1},
|
||||
.VSHRN = { 1316, 1},
|
||||
.VRSHRN = { 1317, 1},
|
||||
.VSHLL = { 1318, 4},
|
||||
.VCLS = { 1322, 6},
|
||||
.VCLZ = { 1328, 6},
|
||||
.VCNT = { 1334, 2},
|
||||
.VREV16 = { 1336, 2},
|
||||
.VREV32 = { 1338, 4},
|
||||
.VREV64 = { 1342, 6},
|
||||
.VEXT = { 1348, 2},
|
||||
.VTBL = { 1350, 4},
|
||||
.VTBX = { 1354, 4},
|
||||
.VTRN = { 1358, 6},
|
||||
.VUZP = { 1364, 5},
|
||||
.VZIP = { 1369, 5},
|
||||
.VDUP = { 1374, 5},
|
||||
.VSWP = { 1379, 2},
|
||||
.VMOV_LANE = { 1381, 3},
|
||||
.VLD1 = { 1384, 8},
|
||||
.VLD2 = { 1392, 3},
|
||||
.VLD3 = { 1395, 2},
|
||||
.VLD4 = { 1397, 2},
|
||||
.VST1 = { 1399, 7},
|
||||
.VST2 = { 1406, 3},
|
||||
.VST3 = { 1409, 2},
|
||||
.VST4 = { 1411, 2},
|
||||
.AESE = { 1413, 1},
|
||||
.AESD = { 1414, 1},
|
||||
.AESMC = { 1415, 1},
|
||||
.AESIMC = { 1416, 1},
|
||||
.SHA1H = { 1417, 1},
|
||||
.SHA1SU0 = { 1418, 1},
|
||||
.SHA1SU1 = { 1419, 1},
|
||||
.SHA1C = { 1420, 1},
|
||||
.SHA1M = { 1421, 1},
|
||||
.SHA1P = { 1422, 1},
|
||||
.SHA256H = { 1423, 1},
|
||||
.SHA256H2 = { 1424, 1},
|
||||
.SHA256SU0 = { 1425, 1},
|
||||
.SHA256SU1 = { 1426, 1},
|
||||
.VJCVT = { 1427, 1},
|
||||
.VSDOT = { 1428, 4},
|
||||
.VUDOT = { 1432, 4},
|
||||
.VDOT = { 1436, 2},
|
||||
.VMMLA = { 1438, 1},
|
||||
.VFMAL = { 1439, 2},
|
||||
.VFMSL = { 1441, 2},
|
||||
.VCMLA = { 1443, 5},
|
||||
.VCADD = { 1448, 2},
|
||||
.VSMMLA = { 1450, 1},
|
||||
.VUMMLA = { 1451, 1},
|
||||
.VUSMMLA = { 1452, 1},
|
||||
.VSUDOT = { 1453, 2},
|
||||
.VUSDOT = { 1455, 4},
|
||||
.VQABS = { 1459, 1},
|
||||
.VQNEG = { 1460, 1},
|
||||
.VMOVX = { 1461, 1},
|
||||
.VINS = { 1462, 1},
|
||||
.VLD2R = { 1463, 1},
|
||||
.VLD3R = { 1464, 1},
|
||||
.VLD4R = { 1465, 1},
|
||||
.VLD1_LANE = { 1466, 3},
|
||||
.VLD2_LANE = { 1469, 3},
|
||||
.VLD3_LANE = { 1472, 3},
|
||||
.VLD4_LANE = { 1475, 3},
|
||||
.VST1_LANE = { 1478, 3},
|
||||
.VST2_LANE = { 1481, 3},
|
||||
.VST3_LANE = { 1484, 3},
|
||||
.VST4_LANE = { 1487, 3},
|
||||
.IT = { 1490, 1},
|
||||
.TT = { 1491, 1},
|
||||
.TTT = { 1492, 1},
|
||||
.TTA = { 1493, 1},
|
||||
.TTAT = { 1494, 1},
|
||||
.SG = { 1495, 1},
|
||||
.BXNS = { 1496, 1},
|
||||
.BLXNS = { 1497, 1},
|
||||
.PAC = { 1498, 1},
|
||||
.PACBTI = { 1499, 1},
|
||||
.AUT = { 1500, 1},
|
||||
.AUTG = { 1501, 1},
|
||||
.BTI = { 1502, 1},
|
||||
.WLS = { 1503, 1},
|
||||
.WLSTP = { 1504, 1},
|
||||
.DLS = { 1505, 1},
|
||||
.DLSTP = { 1506, 1},
|
||||
.LE = { 1507, 1},
|
||||
.LETP = { 1508, 1},
|
||||
.LCTP = { 1509, 1},
|
||||
.BF = { 1510, 1},
|
||||
.BFX = { 1511, 1},
|
||||
.BFL = { 1512, 1},
|
||||
.BFLX = { 1513, 1},
|
||||
.BFCSEL = { 1514, 1},
|
||||
.CX1 = { 1515, 1},
|
||||
.CX1A = { 1516, 1},
|
||||
.CX1D = { 1517, 1},
|
||||
.CX1DA = { 1518, 1},
|
||||
.CX2 = { 1519, 1},
|
||||
.CX2A = { 1520, 1},
|
||||
.CX2D = { 1521, 1},
|
||||
.CX2DA = { 1522, 1},
|
||||
.CX3 = { 1523, 1},
|
||||
.CX3A = { 1524, 1},
|
||||
.CX3D = { 1525, 1},
|
||||
.CX3DA = { 1526, 1},
|
||||
.VCX1 = { 1527, 2},
|
||||
.VCX1A = { 1529, 2},
|
||||
.VCX2 = { 1531, 2},
|
||||
.VCX2A = { 1533, 2},
|
||||
.VCX3 = { 1535, 2},
|
||||
.VCX3A = { 1537, 2},
|
||||
.VPT = { 1539, 1},
|
||||
.VPST = { 1540, 1},
|
||||
.VPSEL = { 1541, 1},
|
||||
.VPNOT = { 1542, 1},
|
||||
.VCTP = { 1543, 1},
|
||||
.VADDV = { 1544, 1},
|
||||
.VADDVA = { 1545, 1},
|
||||
.VADDLV = { 1546, 1},
|
||||
.VADDLVA = { 1547, 1},
|
||||
.VMAXV = { 1548, 1},
|
||||
.VMAXAV = { 1549, 1},
|
||||
.VMINV = { 1550, 1},
|
||||
.VMINAV = { 1551, 1},
|
||||
.VMAXNMV = { 1552, 1},
|
||||
.VMAXNMAV = { 1553, 1},
|
||||
.VMINNMV = { 1554, 1},
|
||||
.VMINNMAV = { 1555, 1},
|
||||
.VABAV = { 1556, 1},
|
||||
.VMLADAV = { 1557, 1},
|
||||
.VMLADAVA = { 1558, 1},
|
||||
.VMLADAVX = { 1559, 1},
|
||||
.VMLADAVAX = { 1560, 1},
|
||||
.VMLALDAV = { 1561, 1},
|
||||
.VMLALDAVA = { 1562, 1},
|
||||
.VMLALDAVX = { 1563, 1},
|
||||
.VMLALDAVAX = { 1564, 1},
|
||||
.VMLSDAV = { 1565, 1},
|
||||
.VMLSDAVA = { 1566, 1},
|
||||
.VMLSDAVX = { 1567, 1},
|
||||
.VMLSDAVAX = { 1568, 1},
|
||||
.VMLSLDAV = { 1569, 1},
|
||||
.VMLSLDAVA = { 1570, 1},
|
||||
.VMLSLDAVX = { 1571, 1},
|
||||
.VMLSLDAVAX = { 1572, 1},
|
||||
.VRMLALDAVH = { 1573, 1},
|
||||
.VRMLALDAVHA = { 1574, 1},
|
||||
.VRMLALDAVHX = { 1575, 1},
|
||||
.VRMLALDAVHAX = { 1576, 1},
|
||||
.VRMLSLDAVH = { 1577, 1},
|
||||
.VRMLSLDAVHA = { 1578, 1},
|
||||
.VRMLSLDAVHX = { 1579, 1},
|
||||
.VRMLSLDAVHAX = { 1580, 1},
|
||||
.VMLAV = { 1581, 1},
|
||||
.VMLAVA = { 1582, 1},
|
||||
.VMLSV = { 1583, 1},
|
||||
.VMLSVA = { 1584, 1},
|
||||
.VCMUL = { 1585, 1},
|
||||
.VHCADD = { 1586, 2},
|
||||
.VBRSR = { 1588, 1},
|
||||
.VSHLC = { 1589, 1},
|
||||
.VDDUP = { 1590, 1},
|
||||
.VIDUP = { 1591, 1},
|
||||
.VDWDUP = { 1592, 1},
|
||||
.VIWDUP = { 1593, 1},
|
||||
.VMOVNB = { 1594, 1},
|
||||
.VMOVNT = { 1595, 1},
|
||||
.VQMOVNB = { 1596, 1},
|
||||
.VQMOVNT = { 1597, 1},
|
||||
.VQMOVUNB = { 1598, 1},
|
||||
.VQMOVUNT = { 1599, 1},
|
||||
.VSHLLB = { 1600, 1},
|
||||
.VSHLLT = { 1601, 1},
|
||||
.VMULLB = { 1602, 1},
|
||||
.VMULLT = { 1603, 1},
|
||||
.VMLALB = { 1604, 1},
|
||||
.VMLALT = { 1605, 1},
|
||||
.VMLSLB = { 1606, 1},
|
||||
.VMLSLT = { 1607, 1},
|
||||
.VSHRNB = { 1608, 1},
|
||||
.VSHRNT = { 1609, 1},
|
||||
.VRSHRNB = { 1610, 1},
|
||||
.VRSHRNT = { 1611, 1},
|
||||
.VQSHRNB = { 1612, 1},
|
||||
.VQSHRNT = { 1613, 1},
|
||||
.VQRSHRNB = { 1614, 1},
|
||||
.VQRSHRNT = { 1615, 1},
|
||||
.VQSHRUNB = { 1616, 1},
|
||||
.VQSHRUNT = { 1617, 1},
|
||||
.VQRSHRUNB = { 1618, 1},
|
||||
.VQRSHRUNT = { 1619, 1},
|
||||
.VQDMLADH = { 1620, 1},
|
||||
.VQDMLADHX = { 1621, 1},
|
||||
.VQDMLSDH = { 1622, 1},
|
||||
.VQDMLSDHX = { 1623, 1},
|
||||
.VQRDMLADH = { 1624, 1},
|
||||
.VQRDMLADHX = { 1625, 1},
|
||||
.VQRDMLSDH = { 1626, 1},
|
||||
.VQRDMLSDHX = { 1627, 1},
|
||||
.VLDRB = { 1628, 2},
|
||||
.VLDRH = { 1630, 2},
|
||||
.VLDRW = { 1632, 2},
|
||||
.VLDRD = { 1634, 2},
|
||||
.VSTRB = { 1636, 2},
|
||||
.VSTRH = { 1638, 2},
|
||||
.VSTRW = { 1640, 2},
|
||||
.VSTRD = { 1642, 2},
|
||||
.VLD20 = { 1644, 1},
|
||||
.VLD21 = { 1645, 1},
|
||||
.VLD40 = { 1646, 1},
|
||||
.VLD41 = { 1647, 1},
|
||||
.VLD42 = { 1648, 1},
|
||||
.VLD43 = { 1649, 1},
|
||||
.VST20 = { 1650, 1},
|
||||
.VST21 = { 1651, 1},
|
||||
.VST40 = { 1652, 1},
|
||||
.VST41 = { 1653, 1},
|
||||
.VST42 = { 1654, 1},
|
||||
.VST43 = { 1655, 1},
|
||||
._COUNT = { 1656, 0},
|
||||
.VMOV = { 806, 33},
|
||||
.VMRS = { 839, 1},
|
||||
.VMSR = { 840, 1},
|
||||
.VLDR = { 841, 2},
|
||||
.VSTR = { 843, 2},
|
||||
.VLDM = { 845, 2},
|
||||
.VSTM = { 847, 2},
|
||||
.VPUSH = { 849, 2},
|
||||
.VPOP = { 851, 2},
|
||||
.VSEL = { 853, 2},
|
||||
.VMAXNM = { 855, 2},
|
||||
.VMINNM = { 857, 2},
|
||||
.VRINTA = { 859, 3},
|
||||
.VRINTN = { 862, 3},
|
||||
.VRINTP = { 865, 3},
|
||||
.VRINTM = { 868, 3},
|
||||
.VRINTR = { 871, 2},
|
||||
.VRINTZ = { 873, 3},
|
||||
.VRINTX = { 876, 3},
|
||||
.VADDL = { 879, 6},
|
||||
.VADDW = { 885, 6},
|
||||
.VSUBL = { 891, 6},
|
||||
.VSUBW = { 897, 6},
|
||||
.VHADD = { 903, 9},
|
||||
.VHSUB = { 912, 9},
|
||||
.VRHADD = { 921, 3},
|
||||
.VQADD = { 924, 11},
|
||||
.VQSUB = { 935, 11},
|
||||
.VMULL = { 946, 11},
|
||||
.VMLAL = { 957, 10},
|
||||
.VMLSL = { 967, 10},
|
||||
.VQDMULL = { 977, 4},
|
||||
.VQDMLAL = { 981, 4},
|
||||
.VQDMLSL = { 985, 4},
|
||||
.VQDMULH = { 989, 8},
|
||||
.VQRDMULH = { 997, 8},
|
||||
.VQRDMLAH = { 1005, 8},
|
||||
.VQRDMLSH = { 1013, 8},
|
||||
.VABA = { 1021, 8},
|
||||
.VABAL = { 1029, 6},
|
||||
.VABD = { 1035, 10},
|
||||
.VABDL = { 1045, 6},
|
||||
.VAND = { 1051, 3},
|
||||
.VBIC = { 1054, 3},
|
||||
.VORR = { 1057, 3},
|
||||
.VORN = { 1060, 3},
|
||||
.VEOR = { 1063, 3},
|
||||
.VBSL = { 1066, 2},
|
||||
.VBIT = { 1068, 2},
|
||||
.VBIF = { 1070, 2},
|
||||
.VMVN = { 1072, 13},
|
||||
.VMOVN = { 1085, 3},
|
||||
.VQMOVN = { 1088, 6},
|
||||
.VQMOVUN = { 1094, 3},
|
||||
.VMOVL = { 1097, 6},
|
||||
.VTST = { 1103, 6},
|
||||
.VCEQ = { 1109, 14},
|
||||
.VCGE = { 1123, 16},
|
||||
.VCGT = { 1139, 16},
|
||||
.VCLE = { 1155, 18},
|
||||
.VCLT = { 1173, 18},
|
||||
.VACGE = { 1191, 2},
|
||||
.VACGT = { 1193, 2},
|
||||
.VACLE = { 1195, 2},
|
||||
.VACLT = { 1197, 2},
|
||||
.VMAX = { 1199, 13},
|
||||
.VMIN = { 1212, 13},
|
||||
.VPMAX = { 1225, 5},
|
||||
.VPMIN = { 1230, 5},
|
||||
.VPADD = { 1235, 5},
|
||||
.VPADDL = { 1240, 6},
|
||||
.VPADAL = { 1246, 4},
|
||||
.VRECPE = { 1250, 4},
|
||||
.VRECPS = { 1254, 2},
|
||||
.VRSQRTE = { 1256, 4},
|
||||
.VRSQRTS = { 1260, 2},
|
||||
.VSHL = { 1262, 9},
|
||||
.VSHR = { 1271, 3},
|
||||
.VSRA = { 1274, 3},
|
||||
.VRSHL = { 1277, 5},
|
||||
.VRSHR = { 1282, 3},
|
||||
.VRSRA = { 1285, 2},
|
||||
.VSLI = { 1287, 2},
|
||||
.VSRI = { 1289, 2},
|
||||
.VQSHL = { 1291, 7},
|
||||
.VQSHRN = { 1298, 1},
|
||||
.VQSHRUN = { 1299, 1},
|
||||
.VQRSHL = { 1300, 16},
|
||||
.VQRSHRN = { 1316, 1},
|
||||
.VQRSHRUN = { 1317, 1},
|
||||
.VSHRN = { 1318, 1},
|
||||
.VRSHRN = { 1319, 1},
|
||||
.VSHLL = { 1320, 4},
|
||||
.VCLS = { 1324, 6},
|
||||
.VCLZ = { 1330, 6},
|
||||
.VCNT = { 1336, 2},
|
||||
.VREV16 = { 1338, 2},
|
||||
.VREV32 = { 1340, 4},
|
||||
.VREV64 = { 1344, 6},
|
||||
.VEXT = { 1350, 2},
|
||||
.VTBL = { 1352, 4},
|
||||
.VTBX = { 1356, 4},
|
||||
.VTRN = { 1360, 6},
|
||||
.VUZP = { 1366, 5},
|
||||
.VZIP = { 1371, 5},
|
||||
.VDUP = { 1376, 5},
|
||||
.VSWP = { 1381, 2},
|
||||
.VLD1 = { 1383, 8},
|
||||
.VLD2 = { 1391, 6},
|
||||
.VLD3 = { 1397, 5},
|
||||
.VLD4 = { 1402, 5},
|
||||
.VST1 = { 1407, 7},
|
||||
.VST2 = { 1414, 6},
|
||||
.VST3 = { 1420, 5},
|
||||
.VST4 = { 1425, 5},
|
||||
.AESE = { 1430, 1},
|
||||
.AESD = { 1431, 1},
|
||||
.AESMC = { 1432, 1},
|
||||
.AESIMC = { 1433, 1},
|
||||
.SHA1H = { 1434, 1},
|
||||
.SHA1SU0 = { 1435, 1},
|
||||
.SHA1SU1 = { 1436, 1},
|
||||
.SHA1C = { 1437, 1},
|
||||
.SHA1M = { 1438, 1},
|
||||
.SHA1P = { 1439, 1},
|
||||
.SHA256H = { 1440, 1},
|
||||
.SHA256H2 = { 1441, 1},
|
||||
.SHA256SU0 = { 1442, 1},
|
||||
.SHA256SU1 = { 1443, 1},
|
||||
.VJCVT = { 1444, 1},
|
||||
.VSDOT = { 1445, 4},
|
||||
.VUDOT = { 1449, 4},
|
||||
.VDOT = { 1453, 2},
|
||||
.VMMLA = { 1455, 1},
|
||||
.VFMAL = { 1456, 2},
|
||||
.VFMSL = { 1458, 2},
|
||||
.VCMLA = { 1460, 5},
|
||||
.VCADD = { 1465, 2},
|
||||
.VSMMLA = { 1467, 1},
|
||||
.VUMMLA = { 1468, 1},
|
||||
.VUSMMLA = { 1469, 1},
|
||||
.VSUDOT = { 1470, 2},
|
||||
.VUSDOT = { 1472, 4},
|
||||
.VQABS = { 1476, 1},
|
||||
.VQNEG = { 1477, 1},
|
||||
.VMOVX = { 1478, 1},
|
||||
.VINS = { 1479, 1},
|
||||
.VLD2R = { 1480, 1},
|
||||
.VLD3R = { 1481, 1},
|
||||
.VLD4R = { 1482, 1},
|
||||
.IT = { 1483, 1},
|
||||
.TT = { 1484, 1},
|
||||
.TTT = { 1485, 1},
|
||||
.TTA = { 1486, 1},
|
||||
.TTAT = { 1487, 1},
|
||||
.SG = { 1488, 1},
|
||||
.BXNS = { 1489, 1},
|
||||
.BLXNS = { 1490, 1},
|
||||
.PAC = { 1491, 1},
|
||||
.PACBTI = { 1492, 1},
|
||||
.AUT = { 1493, 1},
|
||||
.AUTG = { 1494, 1},
|
||||
.BTI = { 1495, 1},
|
||||
.WLS = { 1496, 1},
|
||||
.WLSTP = { 1497, 1},
|
||||
.DLS = { 1498, 1},
|
||||
.DLSTP = { 1499, 1},
|
||||
.LE = { 1500, 1},
|
||||
.LETP = { 1501, 1},
|
||||
.LCTP = { 1502, 1},
|
||||
.BF = { 1503, 1},
|
||||
.BFX = { 1504, 1},
|
||||
.BFL = { 1505, 1},
|
||||
.BFLX = { 1506, 1},
|
||||
.BFCSEL = { 1507, 1},
|
||||
.CX1 = { 1508, 1},
|
||||
.CX1A = { 1509, 1},
|
||||
.CX1D = { 1510, 1},
|
||||
.CX1DA = { 1511, 1},
|
||||
.CX2 = { 1512, 1},
|
||||
.CX2A = { 1513, 1},
|
||||
.CX2D = { 1514, 1},
|
||||
.CX2DA = { 1515, 1},
|
||||
.CX3 = { 1516, 1},
|
||||
.CX3A = { 1517, 1},
|
||||
.CX3D = { 1518, 1},
|
||||
.CX3DA = { 1519, 1},
|
||||
.VCX1 = { 1520, 2},
|
||||
.VCX1A = { 1522, 2},
|
||||
.VCX2 = { 1524, 2},
|
||||
.VCX2A = { 1526, 2},
|
||||
.VCX3 = { 1528, 2},
|
||||
.VCX3A = { 1530, 2},
|
||||
.VPT = { 1532, 1},
|
||||
.VPST = { 1533, 1},
|
||||
.VPSEL = { 1534, 1},
|
||||
.VPNOT = { 1535, 1},
|
||||
.VCTP = { 1536, 1},
|
||||
.VADDV = { 1537, 1},
|
||||
.VADDVA = { 1538, 1},
|
||||
.VADDLV = { 1539, 1},
|
||||
.VADDLVA = { 1540, 1},
|
||||
.VMAXV = { 1541, 1},
|
||||
.VMAXAV = { 1542, 1},
|
||||
.VMINV = { 1543, 1},
|
||||
.VMINAV = { 1544, 1},
|
||||
.VMAXNMV = { 1545, 1},
|
||||
.VMAXNMAV = { 1546, 1},
|
||||
.VMINNMV = { 1547, 1},
|
||||
.VMINNMAV = { 1548, 1},
|
||||
.VABAV = { 1549, 1},
|
||||
.VMLADAV = { 1550, 1},
|
||||
.VMLADAVA = { 1551, 1},
|
||||
.VMLADAVX = { 1552, 1},
|
||||
.VMLADAVAX = { 1553, 1},
|
||||
.VMLALDAV = { 1554, 1},
|
||||
.VMLALDAVA = { 1555, 1},
|
||||
.VMLALDAVX = { 1556, 1},
|
||||
.VMLALDAVAX = { 1557, 1},
|
||||
.VMLSDAV = { 1558, 1},
|
||||
.VMLSDAVA = { 1559, 1},
|
||||
.VMLSDAVX = { 1560, 1},
|
||||
.VMLSDAVAX = { 1561, 1},
|
||||
.VMLSLDAV = { 1562, 1},
|
||||
.VMLSLDAVA = { 1563, 1},
|
||||
.VMLSLDAVX = { 1564, 1},
|
||||
.VMLSLDAVAX = { 1565, 1},
|
||||
.VRMLALDAVH = { 1566, 1},
|
||||
.VRMLALDAVHA = { 1567, 1},
|
||||
.VRMLALDAVHX = { 1568, 1},
|
||||
.VRMLALDAVHAX = { 1569, 1},
|
||||
.VRMLSLDAVH = { 1570, 1},
|
||||
.VRMLSLDAVHA = { 1571, 1},
|
||||
.VRMLSLDAVHX = { 1572, 1},
|
||||
.VRMLSLDAVHAX = { 1573, 1},
|
||||
.VMLAV = { 1574, 1},
|
||||
.VMLAVA = { 1575, 1},
|
||||
.VMLSV = { 1576, 1},
|
||||
.VMLSVA = { 1577, 1},
|
||||
.VCMUL = { 1578, 1},
|
||||
.VHCADD = { 1579, 2},
|
||||
.VBRSR = { 1581, 1},
|
||||
.VSHLC = { 1582, 1},
|
||||
.VDDUP = { 1583, 1},
|
||||
.VIDUP = { 1584, 1},
|
||||
.VDWDUP = { 1585, 1},
|
||||
.VIWDUP = { 1586, 1},
|
||||
.VMOVNB = { 1587, 1},
|
||||
.VMOVNT = { 1588, 1},
|
||||
.VQMOVNB = { 1589, 1},
|
||||
.VQMOVNT = { 1590, 1},
|
||||
.VQMOVUNB = { 1591, 1},
|
||||
.VQMOVUNT = { 1592, 1},
|
||||
.VSHLLB = { 1593, 1},
|
||||
.VSHLLT = { 1594, 1},
|
||||
.VMULLB = { 1595, 1},
|
||||
.VMULLT = { 1596, 1},
|
||||
.VMLALB = { 1597, 1},
|
||||
.VMLALT = { 1598, 1},
|
||||
.VMLSLB = { 1599, 1},
|
||||
.VMLSLT = { 1600, 1},
|
||||
.VSHRNB = { 1601, 1},
|
||||
.VSHRNT = { 1602, 1},
|
||||
.VRSHRNB = { 1603, 1},
|
||||
.VRSHRNT = { 1604, 1},
|
||||
.VQSHRNB = { 1605, 1},
|
||||
.VQSHRNT = { 1606, 1},
|
||||
.VQRSHRNB = { 1607, 1},
|
||||
.VQRSHRNT = { 1608, 1},
|
||||
.VQSHRUNB = { 1609, 1},
|
||||
.VQSHRUNT = { 1610, 1},
|
||||
.VQRSHRUNB = { 1611, 1},
|
||||
.VQRSHRUNT = { 1612, 1},
|
||||
.VQDMLADH = { 1613, 1},
|
||||
.VQDMLADHX = { 1614, 1},
|
||||
.VQDMLSDH = { 1615, 1},
|
||||
.VQDMLSDHX = { 1616, 1},
|
||||
.VQRDMLADH = { 1617, 1},
|
||||
.VQRDMLADHX = { 1618, 1},
|
||||
.VQRDMLSDH = { 1619, 1},
|
||||
.VQRDMLSDHX = { 1620, 1},
|
||||
.VLDRB = { 1621, 2},
|
||||
.VLDRH = { 1623, 2},
|
||||
.VLDRW = { 1625, 2},
|
||||
.VLDRD = { 1627, 2},
|
||||
.VSTRB = { 1629, 2},
|
||||
.VSTRH = { 1631, 2},
|
||||
.VSTRW = { 1633, 2},
|
||||
.VSTRD = { 1635, 2},
|
||||
.VLD20 = { 1637, 1},
|
||||
.VLD21 = { 1638, 1},
|
||||
.VLD40 = { 1639, 1},
|
||||
.VLD41 = { 1640, 1},
|
||||
.VLD42 = { 1641, 1},
|
||||
.VLD43 = { 1642, 1},
|
||||
.VST20 = { 1643, 1},
|
||||
.VST21 = { 1644, 1},
|
||||
.VST40 = { 1645, 1},
|
||||
.VST41 = { 1646, 1},
|
||||
.VST42 = { 1647, 1},
|
||||
.VST43 = { 1648, 1},
|
||||
._COUNT = { 1649, 0},
|
||||
}
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 10 KiB After Width: | Height: | Size: 10 KiB |
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|
Before Width: | Height: | Size: 3.2 KiB After Width: | Height: | Size: 3.2 KiB |
Binary file not shown.
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Binary file not shown.
Binary file not shown.
@@ -188,11 +188,11 @@ run_smoke :: proc() {
|
||||
check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB30FD0)
|
||||
check("VTBL", .VTBL, 0, 0xF3B00800, 0xFFB00F70)
|
||||
check("VRECPE F32 D", .VRECPE, 2, 0xF3BB0500, 0xFFBF0FD0)
|
||||
check("VLD1 1-reg", .VLD1, 0, 0xF4200700, 0xFFF00F00)
|
||||
check("VST1 1-reg", .VST1, 0, 0xF4000700, 0xFFF00F00)
|
||||
check("VLD2 2-reg", .VLD2, 0, 0xF4200800, 0xFFF00F00)
|
||||
check("VLD3 3-reg", .VLD3, 0, 0xF4200400, 0xFFF00F00)
|
||||
check("VLD4 4-reg", .VLD4, 0, 0xF4200000, 0xFFF00F00)
|
||||
check("VLD1 1-reg", .VLD1, 0, 0xF420070F, 0xFFF00F0F)
|
||||
check("VST1 1-reg", .VST1, 0, 0xF400070F, 0xFFF00F0F)
|
||||
check("VLD2 2-reg", .VLD2, 0, 0xF420080F, 0xFFF00F0F)
|
||||
check("VLD3 3-reg", .VLD3, 0, 0xF420040F, 0xFFF00F0F)
|
||||
check("VLD4 4-reg", .VLD4, 0, 0xF420000F, 0xFFF00F0F)
|
||||
check("VMULL.S8", .VMULL, 0, 0xF2800C00, 0xFFB00F50)
|
||||
|
||||
// ---- Thumb-2 ----
|
||||
@@ -550,15 +550,15 @@ run_smoke :: proc() {
|
||||
check("VLD4R", .VLD4R, 0, 0xF4A00F0F, 0xFFB00F0F)
|
||||
|
||||
// ---- NEON single-element lane loads/stores ----
|
||||
check("VLD1_LANE .8", .VLD1_LANE, 0, 0xF4A00000, 0xFFB00C00)
|
||||
check("VLD1_LANE .16", .VLD1_LANE, 1, 0xF4A00400, 0xFFB00C00)
|
||||
check("VLD1_LANE .32", .VLD1_LANE, 2, 0xF4A00800, 0xFFB00C00)
|
||||
check("VLD2_LANE .8", .VLD2_LANE, 0, 0xF4A00100, 0xFFB00D00)
|
||||
check("VLD3_LANE .16", .VLD3_LANE, 1, 0xF4A00600, 0xFFB00D00)
|
||||
check("VLD4_LANE .32", .VLD4_LANE, 2, 0xF4A00B00, 0xFFB00D00)
|
||||
check("VST1_LANE .8", .VST1_LANE, 0, 0xF4800000, 0xFFB00C00)
|
||||
check("VST3_LANE .32", .VST3_LANE, 2, 0xF4800A00, 0xFFB00D00)
|
||||
check("VST4_LANE .16", .VST4_LANE, 1, 0xF4800700, 0xFFB00D00)
|
||||
check("VLD1 lane .8", .VLD1, 5, 0xF4A0000F, 0xFFB00F1F)
|
||||
check("VLD1 lane .16", .VLD1, 6, 0xF4A0040F, 0xFFB00F3F)
|
||||
check("VLD1 lane .32", .VLD1, 7, 0xF4A0080F, 0xFFB00F7F)
|
||||
check("VLD2 lane .8", .VLD2, 3, 0xF4A0010F, 0xFFB00F1F)
|
||||
check("VLD3 lane .16", .VLD3, 3, 0xF4A0060F, 0xFFB00F3F)
|
||||
check("VLD4 lane .32", .VLD4, 4, 0xF4A00B0F, 0xFFB00F7F)
|
||||
check("VST1 lane .8", .VST1, 4, 0xF480000F, 0xFFB00F1F)
|
||||
check("VST3 lane .32", .VST3, 4, 0xF4800A0F, 0xFFB00F7F)
|
||||
check("VST4 lane .16", .VST4, 3, 0xF480070F, 0xFFB00F3F)
|
||||
|
||||
// ---- MVE rounding-to-int (VPADD/VPMAX/VPMIN MVE forms removed - don't exist) ----
|
||||
check("VRINTA MVE", .VRINTA, 2, 0xFFBA0540, 0xFFBB0FD1)
|
||||
|
||||
Reference in New Issue
Block a user