Alexander Zhura
59b09aa559
Impl fix simd arm neon table lookup on be
2026-08-10 14:07:05 +03:00
Alex
1b14ce9453
Impl simd arm neon table lookup
2026-08-08 18:59:07 +03:00
Alexander Zhura
62afbd45f8
Impl simd arm neon table lookup
2026-08-08 18:49:08 +03:00
Jeroen van Rijn
1f5c523844
Merge pull request #7203 from maxrabin/fix/simd-grammar
...
Fix grammar in simd.odin doc comment
2026-08-08 01:58:27 +02:00
Alexander Zhura
1fd3cbb0b5
Impl simd arm neon bit manipulation
2026-08-04 23:50:47 +03:00
Alexander Zhura
cc71be2a5b
Impl fix simd arm sha arch
2026-08-04 00:19:32 +03:00
Max Rabin
e9cb1e7019
Fix grammar in simd.odin doc comment
2026-08-03 22:26:18 +03:00
Alexander Zhura
659ba07cf3
Impl simd arm pmull
2026-08-01 16:22:15 +03:00
Jeroen van Rijn
cfd0c4dc69
Revert "Impl simd arm pmull"
2026-08-01 14:04:22 +02:00
Alexander Zhura
c2bb93ea59
Impl simd arm pmull
2026-08-01 14:20:19 +03:00
Alexander Zhura
91e62c4187
Impl simd arm crc32
2026-07-31 16:17:27 +03:00
kalsprite
98d6e0c26a
ARM chunking logic, improved docs
2026-05-20 17:55:29 -07:00
gingerBill
a91725f305
Add simd.interleave + simd.deinterleave
2026-05-19 21:32:09 +01:00
gingerBill
f231ef0596
Support simd.byte_swap
2026-05-19 15:44:31 +01:00
gingerBill
42d3f78bae
Improve simd.sign_bit code generation
2026-05-19 14:54:39 +01:00
gingerBill
c87d1a3cf6
Comment out the uncompleted stuff
2026-04-08 15:42:40 +01:00
gingerBill
2414f428a5
Add core:simd/x86/avx.odin
2026-04-08 15:37:46 +01:00
gingerBill
6f7226e692
Add intrinsics.simd_pairwise_(add|sub)
2026-04-07 15:45:50 +01:00
gingerBill
6e09ce9a04
intrinsics.to_bits_signed; simd.signbit
2026-04-07 15:25:41 +01:00
gingerBill
5de18d30f3
Add intrinsics.simd_approx_recip and intrinsics.simd_approx_recip_sqrt
2026-04-07 14:35:04 +01:00
gingerBill
885db93e20
Add intrinsics.simd_sums_of_n
2026-04-07 13:18:03 +01:00
gingerBill
ac1b5aea0f
Add intrinsics.simd_odd_even; More core:simd operations
2026-04-07 11:35:20 +01:00
Yawning Angel
9051f5a075
core/simd/x86: Fix _mm_blend_epi16
2026-03-16 15:52:59 +09:00
Yawning Angel
3a59e8c849
core/simd/arm: Add the SHA intrinsics
...
The SHA3 ones aren't in the developer.arm.com documentation.
2026-03-14 14:05:15 +09:00
Yawning Angel
adb2890d2b
core/simd/arm: Formating fixes (NFC)
2026-03-14 14:05:15 +09:00
Yawning Angel
48b1f3b830
core/simd/arm: Initial import
2026-03-13 21:00:42 +09:00
gingerBill
461486ef6c
Fix comments which used /// instead of //
2026-03-11 13:41:27 +00:00
turu
72db43f2d6
correcting SIMD shr examples documentation
2026-03-09 21:33:23 -05:00
Laytan Laats
f6b8e08628
simd: fix typos
2026-01-11 20:21:25 +01:00
gingerBill
adcbfb7861
Add @(require_results) to core:simd procedures where missing
2025-11-22 09:43:40 +00:00
andzdroid
77fa058d43
Fix renamed function call in bit_not
...
xor was renamed to bit_xor
2025-10-10 22:22:53 +01:00
Jeroen van Rijn
7a9ea3ee6d
Further overhaul of package line comments.
2025-10-09 23:05:29 +02:00
Jeroen van Rijn
2bc409eab5
More package lines.
2025-10-09 20:40:13 +02:00
gingerBill
c73bd6f51d
Make Operation: comments unformatted
2025-10-09 11:42:09 +01:00
Jon Lipstate
ecd41b155d
rename table_lookup to runtime_swizzle
2025-07-16 21:54:24 -07:00
Jon Lipstate
019084a17f
table lookup intrinsic
2025-07-05 13:55:14 -07:00
Feoramund
45219f240e
Rename SIMD_IS_EMULATED to capability-affirmative HAS_HARDWARE_SIMD
2025-05-29 17:17:51 -04:00
Feoramund
827a6f9045
Move simd.IS_EMULATED to runtime.SIMD_IS_EMULATED
2025-05-29 15:12:01 -04:00
gingerBill
0cf5b5984d
Merge pull request #5108 from Barinzaya/core-simd-indices-redadd-redmul
...
Alternate `reduce_add`/`reduce_mul` intrinsics
2025-05-06 15:46:49 +01:00
Barinzaya
41bf1ab6dd
Added BMI and BMI2 intrinsics.
...
The BMI ones mostly aren't particularly interesting--they're mostly
trivially representable in-language--but PDEP and PEXT from BMI2 could
be.
2025-05-06 01:44:10 -04:00
Barinzaya
dd5b7852ce
Added alternate reduce-add/reduce-mul intrinsics.
...
The new reduce_add/reduce_mul procs perform the corresponding arithmetic
reduction in different orders than sequential order. These alternative
orders can often offer better SIMD hardware utilization.
Two different orders are added: pair-wise (operating on pairs of
adjacent elements) or bisection-wise (operating element-wise on the
first and last N/2 elements of the vector).
2025-05-05 16:38:45 -04:00
gingerBill
c4719e75fd
Add simd.indices and docs
2025-05-05 11:43:19 +01:00
Jeroen van Rijn
f7c4c80ef3
Fix broken examples in documentation tester.
...
No more:
```
We could not find the procedure "pkg_foo_example :: proc()" needed to test the example created for "pkg.foo"
The following procedures were found:
bar()
```
2025-04-05 16:36:26 +02:00
Yawning Angel
982ab11aa1
core/crypto/sha2: Use hardware SHA224/256 when available (AMD64)
2025-03-23 19:14:33 +09:00
flysand7
70daf40cb1
Fix documentation for simd_shuffle
2025-03-02 20:42:13 +11:00
flysand7
698c510ba7
Merge branch 'master' into docs-simd
2025-03-02 20:05:55 +11:00
Barinzaya
4afedbc051
Added simd_extract_lsbs intrinsic as well.
...
Equivalent to the simd_extract_msbs intrinsic, except it extracts the
least significant bit of each element instead.
2025-02-24 08:49:57 -05:00
Barinzaya
33a3aab791
Added simd_extract_msbs intrinsic.
2025-02-24 08:39:32 -05:00
flysand7
5d290dce06
Merge branch 'simd-docs' into docs-simd
2025-01-21 11:45:51 +11:00
flysand7
b7afbd6d57
Suggestion fixes
2025-01-21 11:15:00 +11:00
