3 Commits

Author	SHA1	Message	Date
Brendan Punsky	5b47f0ca29	rexcode/mips: MSA INSVE + DSP ASE 3-register/compare/shift forms ... MSA INSVE (.B/.H/.W/.D element insert). DSP ASE three-register ops (ADDU/SUBU/MULEQ/MULEU/MULQ/PRECRQ*/PICK/CMPGU, enc {RD,RS,RT}), the variable shifts SHLLV/SHRAV/SHRLV (enc {RD,RT,RS} -- value is Rt, shift is Rs), and the compares CMP/CMPU (.PH/.QB, {RS,RT}). 38 forms reusing the existing GPR R-type slots. Spot-checked byte-exact vs llvm-mc; 281 tests green.	2026-06-18 03:24:20 -04:00
Brendan Punsky	4ab24007b7	rexcode/mips: MSA BIT-shift, element-index, GPR-index, I8 forms ... New MSA_BIT_SHIFT / MSA_ELM_IDX / MSA_I8 encodings (the data-format marker is fixed in the entry bits; the operand drives the low bits; decode infers df from the marker). SLLI/SRAI/SRLI (.B/.H/.W/.D shift), SPLATI/SLDI (element index), SPLAT/SLD (GPR index), VSHF (.B/.H/.W/.D shuffle), and the I8 forms ANDI/ORI/XORI/NORI/BMNZI/BMZI/BSELI.B + SHF.B/H/W. 42 forms. Spot-checked byte-exact vs llvm-mc and decode-clean across all formats; 281 tests green.	2026-06-18 03:17:39 -04:00
Brendan Punsky	307aa2a9dd	rexcode/mips: MSA 3RF/3R/2R/2RF/VEC encode forms (specgen) ... New mips specgen (llvm-mc --triple=mips --mattr=+msa as the bits oracle, big-endian words, empirical masks): vector FP arithmetic/compare FADD/ FSUB/FMUL/FDIV/FMAX/FMIN/FCEQ/FCLE/FCLT/FCNE (.W/.D), dot product DOTP_S/U (.H/.W/.D), count/popcount NLOC/NLZC/PCNT (.B/.H/.W/.D), one-source FP FSQRT/FRSQRT/FRCP/FRINT/FTRUNC_S/U/FFINT_S/U (.W/.D), and bit-select BMNZ/BMZ/BSEL.V. 57 forms reusing the existing WD/WS/WT slots. Spot- checked byte-exact vs llvm-mc and decode-clean; 281 tests green.	2026-06-18 03:11:41 -04:00