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The VFP fixed-point conversions were a handful of forms whose comments named the 32-bit fixed-point variants but whose encodings all had `sx` clear, so they were the 16-bit ones; two of them were duplicates distinguished only by a looser mask. None of them decoded the fraction width at all, because the operand slot had no encoding, so every one of them printed `#0` -- and a `#0` fraction is not what any of these words mean. The block is now the full matrix the architecture defines: three floating-point widths by two fixed-point widths by four directions, twenty-four forms. The fraction is the fixed-point width less the imm4:i field, so the widest fraction is what a zero field encodes. LSR and ASR reach a shift of 32 through a zero field -- a shift of zero would be a MOV, so the encoding spends that value on the one amount five bits cannot otherwise name. Both the standalone mnemonics and the shifted operand of a data-processing instruction printed `#0`, which is not the same instruction; PKHTB dropped its `asr #32` entirely, since a zero amount prints as no shift at all. USAT and USAT16 saturate to an unsigned width of zero to 31 and store it as it stands, unlike SSAT and SSAT16, which store one less than a signed width of one to 32. They had been sharing the signed encoding and so read one too high. The AES and SHA forms carry a bare element size -- `aese.8`, `sha1c.32` -- and had no data type at all. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA